AS4C64M32MD2-25BCN datasheet(8/129 Pages) ALSC

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3. Functional Description

LPDDR2 is a high-speed SDRAM device internally configured as a 8-Bank memory.

These devices contain the following number of bits:

2 Gb has 2,147,483,648 bits

LPDDR2-S4 uses a double data rate architecture on the Command/Address (CA) bus to reduce the number of input

pins in the system. The 10-bit CA bus contains command, address, and Bank information. Each command uses one

clock cycle, during which command information is transferred on both the positive and negative edge of the clock.

LPDDR2-S4 uses a double data rate architecture on the DQ pins to achieve high speed operation. The double data

rate architecture is essentially a 4n prefetch architecture with an interface designed to transfer two data bits per DQ

every clock cycle at the I/O pins. A single read or write access for the LPDDR2-S4 effectively consists of a single 4n-

bit wide, one clock cycle data transfer at the internal SDRAM core and four corresponding n-bit wide, one-half-clock-

cycle data transfers at the I/O pins.

Read and write accesses to the LPDDR2 are burst oriented; accesses start at a selected location and continue for a

programmed number of locations in a programmed sequence.

For LPDDR2-S4 devices, accesses begin with the registration of an Activate command, which is then followed by a

Read or Write command. The address and BA bits registered coincident with the Activate command are used to select

the row and the Bank to be accessed. The address bits registered coincident with the Read or Write command are

used to select the Bank and the starting column location for the burst access.Prior to normal operation, the LPDDR2

must be initialized..

AS4C64M32MD2-25BCN

AS4C128M16MD2-25BCN

Confidential

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Rev.1.0 July 2016

AS4C64M32MD2-25BCN Datasheet(PDF) 8 Page - Alliance Semiconductor Corporation