 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
HT45F5R Datasheet(PDF) 94 Page - Holtek Semiconductor Inc |
|
|
|||||||||||||||||||||||||||||
HT45F5R Datasheet(HTML) 94 Page - Holtek Semiconductor Inc |
|
|
94 / 138 page  Rev. 1.10 94 De�e��e� 1�� �01� Rev. 1.10 95 De�e��e� 1�� �01� HT45F5R Charger ASSP Flash MCU HT45F5R Charger ASSP Flash MCU Bit4~3 SAVRS1~SAVRS0:ADCreferencevoltageselection 00:ADCreferencevoltageonlycomesfromVREF 01:ADCreferencevoltagesimultaneouslycomesfromVREFandAVDD Othervalues:sameas00 Bit2~0 SACKS2~SACKS0:ADCclockrateselectionbit 000:fSYS 001:fSYS/2 010:fSYS/4 011:fSYS/8 100:fSYS/16 101:fSYS/32 110:fSYS/64 111:fSYS/128 A/D Converter Operation TheSTARTbitintheSADC0registerisusedtostarttheA/Dconversion.Whenthemicrocontroller setsthisbitfromlowtohighandthenlowagain,ananalogtodigitalconversioncyclewillbe initiated. TheADBZbitintheSADC0registerisusedtoindicatewhethertheanalogtodigitalconversion processisinprogressornot.Thisbitwillbeautomaticallysetto1bythemicrocontrollerafteran A/Dconversionissuccessfullyinitiated.WhentheA/Dconversioniscomplete,theADBZwillbe clearedto0.Inaddition,thecorrespondingA/Dinterruptrequestflagwillbesetintheinterrupt controlregister,andiftheinterruptsareenabled,anappropriateinternalinterruptsignalwillbe generated.ThisA/DinternalinterruptsignalwilldirecttheprogramflowtotheassociatedA/D internalinterruptaddressforprocessing.IftheA/Dinternalinterruptisdisabled,themicrocontroller canpolltheADBZbitintheSADC0registertocheckwhetherithasbeenclearedasanalternative methodofdetectingtheendofanA/Dconversioncycle. TheclocksourcefortheA/Dconverter,whichoriginatesfromthesystemclockfSYS,canbechosen tobeeitherfSYSorasubdividedversionoffSYS.Thedivisionratiovalueisdeterminedbythe SACKS2~SACKS0bitsintheSADC1register.AlthoughtheA/Dclocksourceisdeterminedbythe systemclockfSYSandbybitsSACKS2~SACKS0,therearesomelimitationsonthemaximumA/D clocksourcespeedthatcanbeselected.AstherecommendedrangeofpermissibleA/Dclockperiod, tADCK,isfrom0.5μsto10μs,caremustbetakenforsystemclockfrequencies.Forexample,asthe systemclockoperatesatafrequencyof8MHz,theSACKS2~SACKS0bitsshouldnotbesetto000, 001or111.DoingsowillgiveA/DclockperiodsthatarelessthantheminimumA/Dclockperiod whichmayresultininaccurateA/Dconversionvalues.Refertothefollowingtableforexamples, wherevaluesmarkedwithanasterisk*showwhere,dependinguponthedevice,specialcaremust betaken,asthevaluesmaybelessthanthespecifiedminimumA/DClockPeriod. fSYS A/D Clock Period (tADCK) SACKS [2:0]=000 (fSYS) SACKS [2:0]=001 (fSYS/2) SACKS [2:0]=010 (fSYS/4) SACKS [2:0]=011 (fSYS/8) SACKS [2:0]=100 (fSYS/16) SACKS [2:0]=101 (fSYS/32) SACKS [2:0]=110 (fSYS/64) SACKS [2:0]=111 (fSYS/128) 1MHz 1μs 2μs 4μs 8μs 16μs * 32μs * 64μs * 128μs * �MHz 500ns 1μs 2μs 4μs 8μs 16μs * 32μs * 64μs * 4MHz �50ns * 500ns 1μs 2μs 4μs 8μs 16μs * 32μs * 8MHz 1�5ns * �50ns * 500ns 1μs 2μs 4μs 8μs 16μs * A/D Clock Period Examples |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
