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DSP56857 Datasheet(PDF) 112 Page - Freescale Semiconductor, Inc |
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DSP56857 Datasheet(HTML) 112 Page - Freescale Semiconductor, Inc |
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112 / 662 page  Block Diagram 5685X Digital Signal Controller User Manual, Rev. 4 4-4 Freescale Semiconductor – Wait mode shuts down the 56800E core, and unnecessary system clock operation. – Run mode supports full part operation. • Controls to enable/disable the 56800E core Wait and Stop instructions • 32-cycle extended chip internal reset • 32-cycle extended Time-of-Day reset (responds only to POR reset) • 32-cycle extended reset for the Clock Generated Module (CGM) • Software initiated reset • Controls to redirect internal data and/or program RAM accesses to the external memory interface • Software Boot mode Control Register, initialized at any reset (except COP reset) from external pins • A hold off output to coordinate peripheral bus transactions with the system bus pipeline • Two 16-bit registers reset only by a power-on reset usable for general purpose software control 4.3 Block Diagram The System Integration Module (SIM) is depicted in Figure 4-1. |
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