PCD6003 datasheet(34/96 Pages) PHILIPS

34 / 96 page

2001 Apr 17

Philips Semiconductors

Product speciﬁcation

Digital telephone answering machine chip

PCD6003

10.7.2

PARALLEL FLASH INTERFACE

If a parallel (4-Mbit) flash memory is chosen Table 26 is

valid.

Table 26 Using P4 with 4-Mbit parallel ﬂash memory

Since parallel flash memory has a much larger addressing

range than the 64 kbytes addressing capability of the

80CL51, additional addressing is done by means of the

P4 SFR and the P4 I/O pad. The P4 SFR is connected to

Port P4 as shown in Table 27.

One pin is necessary to enable and disable the flash

memory to reduce power consumption. Four pins of P4

are necessary to connect various types of flash memories:

• A parallel flash: P4.0 to P4.2, P4.3, RD and WR are

connected to MA[16:18], CEN, OEN and WN

• A serial flash: FSO, FSI, FSC and P4.3 are connected

to DI, DO, SK and CEN pins

• A CAD flash: P4.1 to P4.3, RD, WR are connected to

CLE, ALE, CEN, REN and WEN pins.

RD and WR are available as separate pins. If an access is

done to the AUX RAM (ARD bit of PCON equals logic 0)

the RD and WR will be logic 1 on these pins.

Bits 1, 2 and 4 of Port 4 are set to FSI, FSK and FSO when

a serial flash is selected in the MCSC SFR.

The P4 SFR is defined in Table 28. Bits P4.6 and P4.7 are

not available as addressable bits or port pins.

P4 pin behaviour and configuration is described in more

detail in Section 16.2.

P4.2

P4.1

P4.0

ADDRESS

Bank 0: 00000H to 0FFFFH

Bank 1: 10000H to 1FFFFH

Bank 2: 20000H to 2FFFFH

Bank 3: 30000H to 3FFFFH

Bank 4: 40000H to 4FFFFH

Bank 5: 50000H to 5FFFFH

Bank 6: 60000H to 6FFFFH

Bank 7: 70000H to 7FFFFH

Table 27 P4 pin behaviour (alternative pin functions)

Note

1. The alternative outputs (GPC, FSI, FSO, FSK and LE) are connected with the general purpose outputs via an AND

logic gate. Therefore when using the alternative functions the corresponding port bits have to be set to a logic 1.

10.7.2.1

Port 4 Register (P4)

Table 28 Port 4 Register (SFR address 98H); reset state 1EH

5(1)

43210

−−

P4.5/GPC

P4.4/FSI

P4.3

P4.2/FSO

P4.1/FSK

P4.0/LE

76543210

P4.7

P4.6

P4.5

P4.4

P4.3

P4.2

P4.1

P4.0

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