PCD6003 datasheet(74/96 Pages) PHILIPS

74 / 96 page

2001 Apr 17

Philips Semiconductors

Product speciﬁcation

Digital telephone answering machine chip

PCD6003

16.2.1

PORT 1REGISTER (P1)

The alternative outputs (SDA and SCL) are connected with the general purpose outputs via an AND logic gate. Therefore

when using the alternative functions the corresponding port bits have to be set to a logic 1.

For control of I2C-bus peripherals like for instance EEPROMs and LCD displays, P1.6 and P1.7 can also be used as SDA

and SCL to support I2C-bus. See Section 10.11 on how to activate this alternative function of P1.6 and P1.7. The rest of

Port 1 is defined as general purpose I/O pins as for the standard 80C51 microcontroller.

Table 68 Port 1 Register (SFR address 90H); bit addressable; reset state FFH

Table 69 P1 pin conﬁguration

16.2.2

PORT 3REGISTER (P3)

Port 3 is defined as a set of 8 general purpose I/O pins similar to the standard 80C51 microcontroller except for P3.6 and

P3.7 which do not have the RD and WR functionality (the RD and WR are separate pins). Table 72 gives the different

functions and the corresponding port configurations available on P3.7, P3.6, P3.1 and P3.0. The last column gives the

function and configuration after reset.

Table 70 P3 (B0H) bit assignment; bit addressable; reset state FFH; note 1

Note

1. The alternative outputs (for MSK, IOM) are connected with the general purpose outputs via an AND logic gate.

Therefore when using the alternative functions the corresponding port bits have to be set to a logic 1.

Table 71 P3 pin conﬁguration

Table 72 Port 3.7, 3.6, 3.1 and 3.0 modes and conﬁguration

76543210

P1.7/SDA

P1.6/SCL

P1.5

P1.4/EX6

P1.3/EX5

P1.2/EX4

P1.1/EX3

P1.0/EX2

PORT PINS

CONFIGURATION

P1.7 and P1.6

open-drain

P1.5 to P1.0

quasi-bidirectional

76543210

P3.7/MIN/DI

P3.6/MOUT

2/FSC

P3.5/T1

P3.4/T0

P3.3/EX1N

P3.2/EX0N

P3.1/MOUT

1/DCK

P3.0/MOUT

0/DO

PORT PINS

CONFIGURATION

P3.7, P3.6, P3.1 and P3.0

see Table 72

P3.5 to P3.2

quasi-bidirectional

MSK

IOM

GENERAL PURPOSE I/O PORT

(RESET STATE)

SIGNAL

MASTER

SLAVE

MOUT0

push-pull

open-drain 4 mA

P3.0

quasi-bidirectional

weak pull-up

MOUT1

push-pull

DCK

push-pull

input

P3.1

MOUT2

push-pull

FSC

push-pull

input

P3.6

MIN

input

P3.7

PCD6003 Datasheet(PDF) 74 Page - NXP Semiconductors

PCD6003 Datasheet(HTML) 74 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96

Datasheet Download

Link URL