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HD64F2145 Datasheet(PDF) 333 Page - Renesas Technology Corp |
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HD64F2145 Datasheet(HTML) 333 Page - Renesas Technology Corp |
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333 / 829 page ![]() Rev. 2.0, 08/02, page 293 of 788 12.9.3 Conflict between TCOR Write and Compare-Match If a compare-match occurs during the T2 state of a TCOR write cycle as shown in figure 12.16, the TCOR write takes priority and the compare-match signal is disabled. With TMR_X, a TICR input capture conflicts with a compare-match in the same way as with a write to TCORC. In this case also, the input capture takes priority and the compare-match signal is disabled. Ø Address TCOR address Internal write signal TCNT TCOR NM T1 T2 TCOR write cycle by CPU TCOR write data N N + 1 Compare-match signal Disabled Figure 12.16 Conflict between TCOR Write and Compare-Match |
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