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HD64F2145 Datasheet(PDF) 337 Page - Renesas Technology Corp |
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HD64F2145 Datasheet(HTML) 337 Page - Renesas Technology Corp |
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337 / 829 page  Rev. 2.0, 08/02, page 297 of 788 Section 13 Timer Connection This LSI allows interconnection between a 16-bit free-running timer (FRT) and three 8-bit timer channels (TMR_1, TMR_X, and TMR_Y). This capability can be used to implement complex functions such as PWM decoding and clamp waveform output. 13.1 Features • Five input pins and four output pins, all of which can be designated for phase inversion. Positive logic is assumed for all signals used within the timer connection facility. • An edge-detection circuit is connected to the input pins, simplifying signal input detection. • TMR_X can be used for PWM input signal decoding. • TMR_X can be used for clamp waveform generation. • An external clock signal divided by TMR_1 can be used as the FRT capture input signal. • An internal synchronization signal can be generated using the FRT and TMR_Y. • A signal generated/modified using an input signal and timer connection can be selected and output. TIMC0N01_010020020700 |
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