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HD64F2145 Datasheet(PDF) 331 Page - Renesas Technology Corp |
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HD64F2145 Datasheet(HTML) 331 Page - Renesas Technology Corp |
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331 / 829 page ![]() Rev. 2.0, 08/02, page 291 of 788 12.9 Usage Notes 12.9.1 Conflict between TCNT Write and Clear If a counter clear signal is generated during the T2 state of a TCNT write cycle as shown in figure 12.14, clearing takes priority, so that the counter is cleared and the write is not performed. Ø Address TCNT address Internal write signal TCNT input clock TCNT N H'00 T1 T2 TCNT write cycle by CPU Figure 12.14 Conflict between TCNT Write and Clear |
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