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HD64F2145 Datasheet(PDF) 328 Page - Renesas Technology Corp |
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HD64F2145 Datasheet(HTML) 328 Page - Renesas Technology Corp |
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328 / 829 page ![]() Rev. 2.0, 08/02, page 288 of 788 Input Capture Signal Input Timing: Figure 12.11 shows the timing of the input capture operation. ø TMRIX Input capture signal TCNTX n nn m M m N + 1 N N n + 1 TICRR TICRF Figure 12.11 Timing of Input Capture Operation If the input capture signal is input while TICRR and TICRF are being read, the input capture signal is delayed by one system clock (ø) cycle. Figure 12.12 shows the timing of this operation. ø TMRIX TICRR, TICRF read cycle T1 T2 Input capture signal Figure 12.12 Timing of Input Capture Signal (Input capture signal is input during TICRR and TICRF read) |
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