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HD64F2145 Datasheet(PDF) 325 Page - Renesas Technology Corp |
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HD64F2145 Datasheet(HTML) 325 Page - Renesas Technology Corp |
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325 / 829 page ![]() Rev. 2.0, 08/02, page 285 of 788 12.5.4 Timing of Counter Clear at Compare-Match TCNT is cleared when compare-match A or compare-match B occurs, depending on the setting of the CCLR1 and CCLR0 bits in TCR. Figure 12.8 shows the timing of clearing the counter by a compare-match. Ø N H'00 Compare-match signal TCNT Figure 12.8 Timing of Counter Clear by Compare-Match 12.5.5 TCNT External Reset Timing TCNT is cleared at the rising edge of an external reset input, depending on the settings of the CCLR1 and CCLR0 bits in TCR. The width of the clearing pulse must be at least 1.5 states. Figure 12.9 shows the timing of clearing the counter by an external reset input. Ø Clear signal External reset input pin TCNT N H'00 N – 1 Figure 12.9 Timing of Counter Clear by External Reset Input |
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