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HD64F2145 Datasheet(PDF) 324 Page - Renesas Technology Corp |
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HD64F2145 Datasheet(HTML) 324 Page - Renesas Technology Corp |
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324 / 829 page  Rev. 2.0, 08/02, page 284 of 788 12.5.2 Timing of CMFA and CMFB Setting at Compare-Match The CMFA and CMFB flags in TCSR are set to 1 by a compare-match signal generated when the TCNT and TCOR values match. The compare-match signal is generated at the last state in which the match is true, just when the timer counter is updated. Therefore, when TCNT and TCOR match, the compare-match signal is not generated until the next TCNT input clock. Figure 12.6 shows the timing of CMF flag setting. Ø TCNT N N + 1 TCOR N Compare-match signal CMF Figure 12.6 Timing of CMF Setting at Compare-Match 12.5.3 Timing of Timer Output at Compare-Match When a compare-match signal occurs, the timer output changes as specified by the OS3 to OS0 bits in TCSR. Figure 12.7 shows the timing of timer output when the output is set to toggle by a compare-match A signal. Ø Compare-match A signal Timer output pin Figure 12.7 Timing of Toggled Timer Output by Compare-Match A Signal |
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