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HD64F2145 Datasheet(PDF) 323 Page - Renesas Technology Corp |
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HD64F2145 Datasheet(HTML) 323 Page - Renesas Technology Corp |
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323 / 829 page ![]() Rev. 2.0, 08/02, page 283 of 788 12.5 Operation Timing 12.5.1 TCNT Count Timing Figure 12.4 shows the TCNT count timing with an internal clock source. Figure 12.5 shows the TCNT count timing with an external clock source. The pulse width of the external clock signal must be at least 1.5 system clocks (ø) for a single edge and at least 2.5 system clocks (ø) for both edges. The counter will not increment correctly if the pulse width is less than these values. Ø Internal clock TCNT input clock TCNT N – 1 N N + 1 Figure 12.4 Count Timing for Internal Clock Input Ø External clock input pin TCNT input clock TCNT N – 1 N N + 1 Figure 12.5 Count Timing for External Clock Input (Both Edges) |
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