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HD64F2145 Datasheet(PDF) 304 Page - Renesas Technology Corp |
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HD64F2145 Datasheet(HTML) 304 Page - Renesas Technology Corp |
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304 / 829 page  Rev. 2.0, 08/02, page 264 of 788 ø Address OCRAR (OCRAF) address Internal write signal Compare-match signal FRC Automatic addition is not performed because compare-match signals are disabled. Disabled OCRA N N N+1 OCRAR (OCRAF) Old data New data T1 T2 Write cycle of OCRAR/OCRAF Figure 11.20 Conflict between OCRAR/OCRAF Write and Compare-Match (When Automatic Addition Function is Used) 11.7.4 Switching of Internal Clock and FRC Operation When the internal clock is changed, the changeover may cause FRC to increment. This depends on the time at which the clock is switched (bits CKS1 and CKS0 are rewritten), as shown in table 11.3. When an internal clock is used, the FRC clock is generated on detection of the falling edge of the internal clock scaled from the system clock (ø). If the clock is changed when the old source is high and the new source is low, as in case no. 3 in table 11.3, the changeover is regarded as a falling edge that triggers the FRC clock, and FRC is incremented. Switching between an internal clock and external clock can also cause FRC to increment. |
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