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HD64F2145 Datasheet(PDF) 301 Page - Renesas Technology Corp |
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HD64F2145 Datasheet(HTML) 301 Page - Renesas Technology Corp |
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301 / 829 page ![]() Rev. 2.0, 08/02, page 261 of 788 11.7 Usage Notes 11.7.1 Conflict between FRC Write and Clear If an internal counter clear signal is generated during the state after an FRC write cycle, the clear signal takes priority and the write is not performed. Figure 11.17 shows the timing for this type of conflict. Ø Address FRC address Internal write signal Counter clear signal FRC N H'0000 T1 T2 Write cycle of FRC Figure 11.17 FRC Write-Clear Conflict |
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