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HD64F2145 Datasheet(PDF) 297 Page - Renesas Technology Corp |
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HD64F2145 Datasheet(HTML) 297 Page - Renesas Technology Corp |
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297 / 829 page  Rev. 2.0, 08/02, page 257 of 788 will be transferred (ICRA and ICRC, or ICRB and ICRD) is being read when the input capture input signal arrives, input capture is delayed by one system clock (ø). Figure 11.10 shows the timing when BUFEA = 1. Input capture signal FTIA ø T1 T2 CPU read cycle of ICRA or ICRC Figure 11.10 Buffered Input Capture Timing (BUFEA = 1) 11.5.6 Timing of Input Capture Flag (ICF) Setting The input capture flag, ICFA, ICFB, ICFC, or ICFD, is set to 1 by the input capture signal. The FRC value is simultaneously transferred to the corresponding input capture register (ICRA, ICRB, ICRC, or ICRD). Figure 11.11 shows the timing of setting the ICFA to ICFD flag. Input capture signal ø ICFA to ICFD ICRA to ICRD FRC N N Figure 11.11 Timing of Input Capture Flag (ICFA, ICFB, ICFC, or ICFD) Setting |
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