 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
HD64F2145 Datasheet(PDF) 293 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
HD64F2145 Datasheet(HTML) 293 Page - Renesas Technology Corp |
|
|
293 / 829 page  Rev. 2.0, 08/02, page 253 of 788 11.4 Operation 11.4.1 Pulse Output Figure 11.2 shows an example of 50%-duty pulses output with an arbitrary phase difference. When a compare match occurs while the CCLRA bit in TCSR is set to 1, the OLVLA and OLVLB bits are inverted by software. H'FFFF OCRA OCRB H'0000 FTOA FTOB Counter clear FRC Figure 11.2 Example of Pulse Output 11.5 Operation Timing 11.5.1 FRC Increment Timing Figure 11.3 shows the FRC increment timing with an internal clock source. Figure 11.4 shows the increment timing with an external clock source. The pulse width of the external clock signal must be at least 1.5 system clocks (ø). The counter will not increment correctly if the pulse width is shorter than 1.5 system clocks (ø). ø Internal clock FRC input clock FRC N – 1 N + 1 N Figure 11.3 Increment Timing with Internal Clock Source |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
