HD64F2145 datasheet(291/829 Pages) RENESAS

291 / 829 page

Rev. 2.0, 08/02, page 251 of 788

Bit

Bit Name

Initial Value

R/W

Description

CKS1

CKS0

R/W

Clock Select 1, 0

Select clock source for FRC.

00: ø/2 internal clock source

01: ø/8 internal clock source

10: ø/32 internal clock source

11: External clock source (counting at FTCI rising edge)

11.3.9

Timer Output Compare Control Register (TOCR)

TOCR enables output from the output compare pins, selects the output levels, switches access

between output compare registers A and B, controls the ICRD and OCRA operating modes, and

switches access to input capture registers A, B, and C.

Bit

Bit Name

Initial Value

R/W

Description

ICRDMS

R/W

Input Capture D Mode Select

Specifies whether ICRD is used in the normal operating

mode or in the operating mode using OCRDM.

0: The normal operating mode is specified for ICRD

1: The operating mode using OCRDM is specified for

ICRD

OCRAMS

R/W

Output Compare A Mode Select

Specifies whether OCRA is used in the normal

operating mode or in the operating mode using OCRAR

and OCRAF.

0: The normal operating mode is specified for OCRA

1: The operating mode using OCRAR and OCRAF is

specified for OCRA

ICRS

R/W

Input Capture Register Select

The same addresses are shared by ICRA and OCRAR,

by ICRB and OCRAF, and by ICRC and OCRDM. The

ICRS bit determines which registers are selected when

the shared addresses are read from or written to. The

operation of ICRA, ICRB, and ICRC is not affected.

0: ICRA, ICRB, and ICRC are selected

1: OCRAR, OCRAF, and OCRDM are selected

HD64F2145 Datasheet(PDF) 291 Page - Renesas Technology Corp

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