MCP48CMB02 datasheet(19/106 Pages) MICROCHIP

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 2019 Microchip Technology Inc.

DS20006160A-page 19

MCP48CXBXX

FIGURE 1-6:

SPI Timing Waveform (Mode = 00).

TABLE 1-5:

SPI REQUIREMENTS (MODE = 00)

#Characteristic(2)

Sym.

Min.

Max. Units

Conditions

—

SCK Input Frequency

FSCK

—25

MHz VDD = 2.7V to 5.5V -

Read command,

CL =20 pF

—50

MHz VDD = 2.7V to 5.5V -

Write commands,

CL =20pF

—10

MHz VDD = 1.8V to 2.7V

CS Active (VIL or VIHH) to SCK Input

TcsA2scH

—

SCK Input High Time

TscH

—

VDD = 2.7V to 5.5V

—

VDD = 1.8V to 2.7V

SCK Input Low Time

TscL

—

VDD = 2.7V to 5.5V

—

VDD = 1.8V to 2.7V

SDI Input Valid to SCK

 Edge (Setup Time)

TDIV2scH

—

SCK

 Edge to SDI Input Invalid (Hold Time)

TscH2DIL10

—

CS Inactive (VIH) to SDO Output

High-Impedance

TcsH2DOZ—

Note 1

SCK

 Edge to SDO Data Output Valid

TscL2DOV—

VDD = 2.7V to 5.5V

—35

VDD = 1.8V to 2.7V

CS Active (VIL) to SDO Data Output Valid

TcsL2DOV

—

2.7V to 5.5V

—

1.8V to 2.7V

SCK

 Edge to CS Inactive (VIH) (Hold Time)

TscH2csI

—

VDD = 2.7V to 5.5V

—

VDD = 1.8V to 2.7V

CS Input High Time

TcsA2csI

—

Delay from HVC VIHH to First Command

Byte(1)

—0

—

Note 1:

This specification is ensured by design.

This parameter is ensured by characterization.

SCK

SDO

SDI

75, 76

MSb

BIT6 - - - - - -1

LSb

MSb IN

BIT6 - - - -1

LSb IN

VIH

VIL

VIH

VIHH

VIH

HVC

Note: HVC pin must be at VIHH until MTP Write cycle completes

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