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MCP48CMB02 Datasheet(PDF) 73 Page - Microchip Technology |
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MCP48CMB02 Datasheet(HTML) 73 Page - Microchip Technology |
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73 / 106 page ![]() 2019 Microchip Technology Inc. DS20006160A-page 73 MCP48CXBXX 7.6 Read Command The Read command is a 24-bit command. The Read command can be issued to both the volatile and nonvolatile memory locations. The format of the command is shown in Figure 7-4. The first 7 bits of the Read command determine the address and the command. The 8th clock will output the CMDERR bit on the SDO pin. For the remaining 16 clocks, the device will transmit the data bits of the specified address (AD4:AD0). Figure 7-4 shows the SDI and SDO information for a Read command. During an MTP write cycle, the Read command can only be issued to the volatile memory locations. By reading the Status register, the Host Controller can determine when the write cycle has been completed (via the state of the MTPMA bit). 7.6.1 SINGLE READ The read operation requires that the CS pin be in the Active state (VIL). Typically, the CS pin will be in the Inactive state (VIH) and is driven to the Active state (VIL). The 24-bit Read command (Command Byte and Data Word) is then clocked in on the SCK and SDI pins. The SDO pin starts driving high (VIH) when the CS goes active and starts driving data on the 8th bit (CMDERR bit); the addressed data comes out on the 9th through 24th clocks. FIGURE 7-4: Read Single Memory Location Command - SDI and SDO States. 12-bit data 10-bit data 8-bit data SDI AD 4 AD 3 AD 2 AD 1 AD 0 C 1 C 0 X X X X X D 11 D 10 D 09 D 08 D 07 D 06 D 05 D 04 D 03 D 02 D 01 D 00 ** ** * 1 1 * * * * * * * * * * * * * * * * * SDO 11 11 11 1 1 00 00 dd dd dd dd dd dd Valid(1) 11 11 11 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Invalid(2) Note 1: The Data bits depend on the resolution of the device: 12-bit = D11:D00, 10-bit = D09:D00, and 8-bit = D07:D00. The unimplemented bits are output as ‘0’ and data are right justified for easy Host Controller operation (no data manipulation after reading the register value). 2: If an Error Condition occurs (CMDERR = ‘0’), all the following SDO bits will be output as ‘0’ until the CMDERR condition is cleared (the CS pin is forced to the Inactive state). |
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