MCP48CMB02 datasheet(61/106 Pages) MICROCHIP

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DS20006160A-page 61

MCP48CXBXX

5.4

Latch Pin (LAT)

The Latch pin controls when the volatile DAC register

value is transferred to the DAC wiper. This is useful for

applications that need to synchronize the wiper(s)

updates to an external event, such as zero crossing or

updates to the other wipers on the device. The LAT pin

is asynchronous to the serial interface operation.

When the LAT pin is high, transfers from the volatile DAC

When the LAT pin is low, the volatile DAC register value

is transferred to the DAC wiper.

Figure 5-8 shows the interaction of the LAT pin and the

loading of the DAC wiper x (from the volatile DAC

is held low, the corresponding DAC wiper is updated as

soon as the volatile DAC register value is updated.

The LAT pin allows the DAC wiper to be updated to an

external event and to have multiple DAC chan-

nels/devices update at a common event.

FIGURE 5-8:

LAT and DAC Interaction.

Since the DAC wiper x is updated from the volatile DAC

LAT pin can be updated synchronously.

If the application does not require synchronization, then

this signal should be tied low.

Figure 5-9 shows two cases of using the LAT pin to

control when the wiper register is updated relative to

the value of a sine wave signal.

FIGURE 5-9:

Example Use of LAT Pin Operation.

5.5

Power-Down Operation

To allow the application to conserve power when DAC

operation is not required, three Power-Down modes

are available. On devices with multiple DACs, each

DAC’s Power-Down mode is individually controllable.

All Power-Down modes do the following:

• Turn off most of the DAC module’s internal circuits

• Op amp is powered down and the VOUT pin

becomes high-impedance

• Retain the value of the volatile DAC register and

configuration bits

Depending on the selected Power-Down mode, the

following will occur:

•VOUT pin is switched to one of the two resistive

pull-downs:

-100 k

 (typical)

-1 k

 (typical)

Note:

This allows both the volatile DAC0 and

DAC1 registers to be updated while the

LAT pin is high, and to have outputs

synchronously updated as the LAT pin is

driven low.

Write command

Vol. DAC register x

DAC wiper x

24 Clocks

LAT

SYNC

Transfer

Serial Shift reg.

Data

(internal signal)

LAT SYNC

Transfer

Data

Comment

No Transfer

Vol. DAC register x

 DAC wiper x

No Transfer

Case 1: Zero Crossing of Sine Wave to update the volatile DAC0 register (using LAT pin)

Case 2: Fixed point Crossing of Sine Wave to update the volatile DAC0 register (using LAT pin)

Indicates where LAT pin pulses are active (volatile DAC0 register updated)

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