MCP48CMB02 datasheet(62/106 Pages) MICROCHIP

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MCP48CXBXX

DS20006160A-page 62

 2019 Microchip Technology Inc.

The Power-Down configuration bits (PD1:PD0) control

the power-down operation (Table 5-4).

TABLE 5-4:

POWER-DOWN BITS AND

OUTPUT RESISTIVE LOAD

There is a delay (TPDD) between the PD1:PD0 bits

changing from ‘00’ to either ‘01’, ‘10’ or ‘11’ and the op

amp no longer driving the VOUT output, and the

pull-down resistors sinking current.

In any of the Power-Down modes where the VOUT pin

is not externally connected (sinking or sourcing cur-

rent), as the number of DACs increases, the device’s

power-down current will also increase.

Table 5-6 shows the current sources for the DAC based

on the selected source of the DAC’s reference voltage

and if the device is in normal operating mode or one of

the Power-Down modes.

The power-down bits are modified by using a write

command to the volatile Power-Down register or a

POR

event,

which

transfers

the

nonvolatile

Power-Down Register to the volatile Power-Down

Section 7.0 “Device Commands” describes the SPI

command for writing the power-down bits.

5.5.1

EXITING POWER-DOWN

The following event changes the PD1:PD0 bits to ‘00’

and therefore exits the Power-Down mode. This is any

SPI Write command where the PD1:PD0 bits are ‘00’.

When the device exits Power-Down mode, the

following occurs:

• Disabled internal circuits are turned on

• Resistor ladder is connected to the selected

reference voltage (VRL)

• Selected pull-down resistor is disconnected

•The VOUT output is driven to the voltage

represented by the volatile DAC register’s value

and configuration bits

DAC Wiper register and DAC Wiper value may be

different due to the DAC Wiper register being modified

while the LAT pin was driven to (and remaining at) VIH.

The VOUT output signal requires time as these circuits

are powered-up and the output voltage is driven to the

specified value as determined by the volatile DAC

PD1

PD0

Function

Normal operation

 resistor to ground

100 k

 resistor to ground

Open circuit

TABLE 5-5:

DAC CURRENT SOURCES

Device

VDD

Current

Source

PDxB:xA = ‘00’,

VREFxB:xA =

PDxB:xA

 ‘00’,

VREFxB:xA =

00 01

11 00

Output

Op Amp

Resistor

Ladder

N(1)

VREF

Selection

Buffer

Band Gap

N N(2) Y(2) N(2) N(2)

Note 1:

The current is sourced from the VREF pin,

not the device VDD.

If DAC0 and DAC1 are in one of the

Power-Down modes, MTP write

operations are not recommended.

Note 1: The SPI serial interface circuit is not

affected by the Power-Down mode. This

circuit remains active in order to receive

any command that might come from the

SPI Master device.

Note:

Since the op amp and Resistor Ladder

were powered off (0V), the op amp’s input

voltage (VW) can be considered 0V. There

is a delay (TPDE) between the PD1:PD0

bits updating to ‘00’ and the op amp

driving the VOUT output. The op amp’s

settling time (from 0V) needs to be taken

into account to ensure the VOUT voltage

reflects the selected value.

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