MCP48CMB02 datasheet(59/106 Pages) MICROCHIP

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DS20006160A-page 59

MCP48CXBXX

The volatile G bit value can be modified by:

• POR event

• BOR event

• SPI Write commands

5.3.2

OUTPUT VOLTAGE

The volatile DAC register values, along with the

device’s configuration bits, control the analog VOUT

voltage. The volatile DAC register’s value is unsigned

binary. The formula for the output voltage is provided in

Equation 5-2. Examples of volatile DAC register values

and the corresponding theoretical VOUT voltage for the

MCP48CXBXX devices are shown in Table 5-6.

EQUATION 5-2:

CALCULATING OUTPUT

VOLTAGE (VOUT)

When Gain = 2 (VRL =VREF), if VREF >VDD/2, the VOUT

voltage is limited to VDD. So if VREF =VDD, the VOUT

voltage does not change for volatile DAC register values

mid-scale and greater, since the output amplifier is at

full-scale output.

The following events update the DAC register value

and therefore the analog voltage output (VOUT):

• Power-on Reset

• Brown-out Reset

• SPI Write command (to volatile registers)

Next, the VOUT voltage starts driving to the new value

after the event has occurred.

5.3.3

OUTPUT SLEW RATE

Figure 5-6 shows an example of the slew rate of the

VOUT pin. The slew rate can be affected by the

characteristics of the circuit connected to the VOUT pin.

FIGURE 5-6:

VOUT Pin Slew Rate.

5.3.3.1

Small Capacitive Load

With a small capacitive load, the output buffer’s current

is not affected by the capacitive load (CL). But still, the

VOUT pin’s voltage is not a step transition from one out-

put value (DAC register value) to the next output value.

The change of the VOUT voltage is limited by the output

buffer’s characteristics, so the VOUT pin voltage will

have a slope from the old voltage to the new voltage.

This slope is fixed for the output buffer, and is referred

to as the buffer slew rate (SRBUF).

5.3.3.2

Large Capacitive Load

With a larger capacitive load, the slew rate is

determined by two factors:

• The output buffer’s short-circuit current (ISC)

•The VOUT pin’s external load

IOUT cannot exceed the output buffer’s short-circuit

current (ISC), which fixes the output buffer slew rate

(SRBUF). The voltage on the capacitive load (CL), VCL

changes at a rate proportional to IOUT, which fixes a

capacitive load slew rate (SRCL).

So the VCL voltage slew rate is limited to the slower of

the output buffer’s internally set slew rate (SRBUF) and

the capacitive load slew rate (SRCL).

5.3.4

DRIVING RESISTIVE AND

CAPACITIVE LOADS

The VOUT pin can drive up to 100 pF of capacitive load

in parallel with a 5 k

 resistive load (to meet electrical

specifications). VOUT drops slowly as the load resis-

tance decreases after about 3.5 k

. It is recommended

to use a load with RL greater than 2 k.

Refer to the Characterization Data documents for a

detailed VOUT vs. Resistive Load characterization

graph.

TABLE 5-2:

OUTPUT DRIVER GAIN

Gain Bit

Gain

Comment

Limits VREF pin voltages

relative to device VDD voltage

Where:

# Resistors in R-Ladder = 4096 (MCP48CXB2X)

1024 (MCP48CXB1X)

256 (MCP48CXB0X)

VOUT

VRL DAC Register Value



# Resistor in Resistor Ladder

----------------------------------------------------------------------Gain



Time

DACx = A

VOUT(A)

VOUT(B)

DACx = B

Slew Rate

VOUT B



VOUT A



–

T

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