MCP48CMB02 datasheet(98/106 Pages) MICROCHIP

98 / 106 page

MCP48CXBXX

DS20006160A-page 98

 2019 Microchip Technology Inc.

B.5

Zero-Scale Error (EZS)

The Zero-Scale Error (see Figure B-2) is the difference

between the ideal and measured VOUT voltage with the

DAC register code equal to 000h (Equation B-3). The

error is dependent on the resistive load on the VOUT pin

(and where that load is tied to, such as VSS or VDD). For

loads (to VDD) greater than specified, the Zero-Scale

Error is greater.

The error in bits is determined by the theoretical voltage

step size to give an error in LSb.

EQUATION B-3:

ZERO SCALE ERROR

B.6

Total Unadjusted Error (ET)

The Total Unadjusted Error (ET) is the difference

between the ideal and measured VOUT voltage.

Typically, calibration of the output voltage is

implemented to improve the system’s performance.

The error in bits is determined by the theortical voltage

step size to give an error in LSb.

Equation B-4 shows the Total Unadjusted Error

calculation

EQUATION B-4:

TOTAL UNADJUSTED

ERROR CALCULATION

B.7

Offset Error (EOS)

The Offset Error is the delta voltage of the VOUT

voltage from the ideal output voltage at the specified

code. This code is specified where the output amplifier

is in the linear operating range; for the MCP48CXBXX

we specify code 64 (decimal). Offset Error does not

include gain error, which is illustrated in Figure B-2.

This error is expressed in mV. Offset Error can be

negative or positive. The error can be calibrated by

software in application circuits.

FIGURE B-2:

OFFSET ERROR (ZERO

GAIN ERROR).

B.8

Offset Error Drift (EOSD)

The Offset Error Drift is the variation in Offset Error due

to a change in ambient temperature. The Offset Error

Drift is typically expressed in ppm/°C or µV/°C.

B.9

Gain Error (EG)

Gain Error is a calculation based on the ideal slope

using the voltage boundaries for the linear range of the

output driver (e.g., code 64 and code 4032) (see

Figure B-3). The Gain Error calculation nullifies the

device’s Offset Error.

The Gain Error indicates how well the slope of the

actual transfer function matches the slope of the ideal

transfer function. The Gain Error is usually expressed

as a percentage of full-scale range (% of FSR) or in

LSb. FSR is the ideal full-scale voltage of the DAC (see

Equation B-5).

Where:

EFS is expressed in LSb.

VOUT(@ZS) is the VOUT voltage when the DAC

VLSb(IDEAL) is the theoretical voltage step size.

EZS

VOUT(@ZS)

VLSb(IDEAL)

----------------------------

Where:

ET is expressed in LSb.

VOUT_Actual(@code) = The measured DAC

output voltage at the

specified code

VOUT_Ideal(@code) = The calculated DAC

output voltage at the

specified code

( code * VLSb(Ideal) )

VLSb(Ideal) =VREF/# Steps

12-bit = VREF/4096

10-bit = VREF/1024

8-bit = VREF/256

VOUT_Actual(@code) VOUT_Ideal(@code)

–



VLSb Ideal



--------------------------------------------------------------------------------------------------

Ideal Transfer

Actual

DAC Input Code

Zero-Scale

Error (EZS)

Offset

Function

4032

Error (EOS)

Transfer

Function

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