MCP48CMB02 datasheet(71/106 Pages) MICROCHIP

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DS20006160A-page 71

MCP48CXBXX

7.5.1

SINGLE WRITE TO VOLATILE

MEMORY

The write operation requires that the CS pin be in the

Active state (VIL). Typically, the CS pin is in the Inac-

tive state (VIH) and is driven to the Active state (VIL).

The 24-bit Write command (Command Byte and Data

Bytes) is then clocked in on the SCK and SDI pins.

Once all 24 bits have been received, the specified

volatile address is updated. A write will not occur if the

Write command isn’t exactly 24 clocks pulses. This

protects against system issues from corrupting the

nonvolatile memory locations.

Figure 7-2 shows the waveform for a single write.

7.5.2

SINGLE WRITE TO NONVOLATILE

MEMORY

The sequence to write to a single nonvolatile memory

location is the same as a single write to volatile

memory with the exception that before the command,

the HVC pin must be driven to VIHH. After the

command, the CS pin is driven inactive (VIH), which

then starts the MTP write cycle (twc). The HVC pin

must remain at the VIHH level until the completion of

the MTP write cycle.

A write cycle will not start if the write command isn’t

exactly 24 clock’s pulses. This protects against system

issues from corrupting the nonvolatile memory

locations.

After the CS pin is driven inactive (VIH), the serial

interface may immediately be re-enabled by driving

the CS pin to the Active state (VIL).

During an MTP write cycle, only serial commands to

volatile memory are accepted. All other serial

commands are ignored until the MTP write cycle (twc)

is completed. The MTPMA bit in the Status register

indicates the status of an MTP Write Cycle.

Once a Write command to a nonvolatile memory

location has been received, NO other SPI commands

should be received before the CS pin transitions to the

Inactive state (VIH) or a Command Error (CMDERR)

on the current SPI command occurs.

The write to a Nonvolatile Memory command has the

same format as the write to a Volatile Memory

command (see Figure 7-2).

FIGURE 7-2:

Write Single Memory Location Command - SDI and SDO States.

12-bit data

10-bit data

8-bit data

SDI

SDO

11 Valid(2)

0 Invalid(3)

Note 1: For Write commands addressing the DAC Wiper Registers, the Data bits depend on the

resolution of the device: 12-bit = D11:D00, 10-bit = D09:D00, and 8-bit = D07:D00.

Data are right justified for easy Host Controller operation (no data manipulation before

transmitting the desired value). The unimplemented bits are ignored.

2: After a valid memory address and a Write command byte are received (CMDERR = ‘1’), all

the following SDO bits will be output as ‘1’.

3: If an Error Condition occurs (CMDERR = ‘0’), all the following SDO bits will be output as ‘0’

until the CMDERR condition is cleared (the CS pin is forced to the Inactive state).

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