MCP48CMB02 datasheet(60/106 Pages) MICROCHIP

60 / 106 page

MCP48CXBXX

DS20006160A-page 60

 2019 Microchip Technology Inc.

Driving large capacitive loads can cause stability

problems for voltage feedback output amplifiers. As the

load capacitance increases, the feedback loop’s phase

margin decreases and the closed-loop bandwidth is

reduced. This produces gain peaking in the frequency

response with overshoot and ringing in the step

response. That is, since the VOUT pin’s voltage does

not quickly follow the buffer’s input voltage (due to the

large capacitive load), the output buffer will overshoot

the desired target voltage. Once the driver detects this

overshoot, it compensates by forcing it to a voltage

below the target. This causes voltage ringing on the

VOUT pin.

So, when driving large capacitive loads with the output

buffer, a small series resistor (RISO) at the output (see

Figure 5-7) improves the output buffer’s stability

(feedback loop’s phase margin) by making the output

load resistive at higher frequencies. The bandwidth will

be generally lower than the bandwidth with no

capacitive load.

FIGURE 5-7:

Circuit to Stabilize Output

Buffer for Large Capacitive Loads (CL).

The RISO resistor value for your circuit needs to be

selected. The resulting frequency response peaking

and step response overshoot for this RISO resistor

value should be verified on the bench. Modify the

RISO’s resistance value until the output characteristics

meet your requirements.

A method to evaluate the system’s performance is to

inject a step voltage on the VREF pin and observe the

VOUT pin’s characteristics.

5.3.5

STEP VOLTAGE (VS)

The Step Voltage depends on the device resolution and

the calculated output voltage range. 1 LSb is defined

as the ideal voltage difference between two successive

codes. The step voltage can easily be calculated by

using Equation 5-3 (the DAC register value is equal to

1). Theoretical Step Voltages are shown in Table 5-3 for

several VREF voltages.

EQUATION 5-3:

VS CALCULATION

Gain

VOUT

RISO

VCL

Note:

Additional insight into circuit design for

driving capacitive loads can be found in

AN884 – “Driving Capacitive Loads With

Op Amps” (DS00000884).

Where:

# Resistors in R-Ladder = 4096

(12-bit)

1024

(10-bit)

256

(8-bit)

VRL

# Resistor in Resistor Ladder

----------------------------------------------------------------------Gain



TABLE 5-3:

THEORETICAL STEP VOLTAGE (VS)(1)

Step

Voltage

VREF

#bits

5.0

2.7

1.8

1.5

1.0

1.22 mV

659 uV

439 uV

366 uV

244 uV

12-bit

4.88 mV

2.64 mV

1.76 mV

1.46 mV

977 uV

10-bit

19.5 mV

10.5 mV

7.03 mV

5.86 mV

3.91 mV

8-bit

Note 1: When Gain = 1X, VFS = VRL, and VZS = 0V.

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