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MCP48CMB02 Datasheet(PDF) 69 Page - Microchip Technology |
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MCP48CMB02 Datasheet(HTML) 69 Page - Microchip Technology |
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69 / 106 page ![]() 2019 Microchip Technology Inc. DS20006160A-page 69 MCP48CXBXX 7.0 DEVICE COMMANDS The MCP48CXBXX’s SPI command format supports 32 memory address locations and two commands. The command may have two modes. These are: • Normal Serial Commands • MTP Programming (HV) Serial Commands Normal serial commands are those where the HVC pin is driven to either VIH or VIL. With High-Voltage Serial commands, the HVC pin is driven to 7.5V. These commands are shown in Table 7-1. Table 7-2 shows an overview of all the SPI commands and their interaction with other device features. The 24-bit commands (Read Command and Write Command) contain a Command Byte and a Data Word. The Command Byte contains one reserved bit, see Figure 7-1. TABLE 7-1: COMMAND BITS OVERVIEW FIGURE 7-1: 24-bit SPI Command Format. Bit States C1:C0 Command # of Bits Normal or HV 11 Read Data 24-Bits Normal only(1) 00 Write Data 24-Bits Both 01 Reserved — — 10 Reserved — — Note 1: Reading from the NV memory locations will return the shadow RAM value of the NV memory, not the NV memory contents. Once a write cycle starts, no other com- mands accessing NV memory locations are allowed. Command Byte Data Word (2 bytes) Legend: AD 4 AD 3 AD 2 AD 1 AD 0 C 1 C 0 X X X X X D 11 D 10 D 09 D 08 D 07 D 06 D 05 D 04 D 03 D 02 D 01 D 00 AD n Memory Address C n Command Bits D nn Data Bits X Reserved TABLE 7-2: SPI COMMANDS - NUMBER OF CLOCKS Command # of Bit Clocks(2) Data Update Rate (8-bit/10-bit/12-bit) (Data Words/Second) Comments Operation Code Mode (1) C1 C0 HV (4,7) 1MHz 10 MHz 50 MHz Write Command(3,6) 00 Y Single 24 41,666 416,666 2,083,333 00 N Continuous 24 * n 41,666 416,666 2,083,333 For 10 data words Read Command(5) 11 N Random 24 41,666 416,666 2,083,333 11 N Continuous 24 * n 41,666 416,666 2,083,333 For 10 data words Note 1: Nonvolatile registers can only use the Single mode. 2: “n” indicates the number of times the command operation is to be repeated. 3: The registers are updated after the 24th clock bit or after the CS rising, depending on mode. 4: If the state of the HVC pin is VIHH, then the command is ignored, but a Command Error condition (CMDERR) will NOT be generated. 5: This command is useful to determine when an MTP programming cycle has completed. 6: This command can be either normal voltage or high voltage. 7: The MTP write cycle starts after the CS rising edge. A High-Voltage command requires the HVC pin to be at VIHH for the entire command, until the completion of the MTP write cycle. |
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