MCP48CMB02 datasheet(43/106 Pages) MICROCHIP

43 / 106 page

 2019 Microchip Technology Inc.

DS20006160A-page 43

MCP48CXBXX

4.0

GENERAL DESCRIPTION

The MCP48CXBX1 devices are single-channel voltage

output devices.

The MCP48CXBX2 devices are dual-channel voltage

output devices.

These devices are offered with 8-bit (MCP48CXB0X),

10-bit (MCP48CXB1X) and 12-bit (MCP48CXB2X)

resolutions.

The

family

offers

two

memory

options:

the

MCP48CVBXX devices have a volatile memory, while

the MCP48CMBXX have a 32-times programmable

nonvolatile memory (MTP).

All devices include an SPI serial interface and a write

latch (LAT) pin to control the update of the analog

output voltage value from the value written in the

volatile DAC output register.

The devices use a resistor ladder architecture. The

resistor

ladder

DAC

driven

from

software-selectable voltage reference source. The

source can be either the device’s internal VDD, an

external VREF pin voltage (buffered or unbuffered) or

an internal band gap voltage source.

The DAC output is buffered with a low power and

precision output amplifier. This output amplifier

provides a rail-to-rail output with low offset voltage and

low noise. The gain (1X or 2X) of the output buffer is

software configurable.

The devices operate from a single supply voltage. This

voltage is specified from 2.7V to 5.5V for full specified

operation, and from 1.8V to 5.5V for digital operation.

The device operates between 1.8V and 2.7V, but

some device parameters are not specified.

The

MCP48CMBXX

devices

also

have

user-programmable nonvolatile configuration memory

(MTP). This allows the device’s desired POR values to

be saved. The device also has general purpose MTP

memory

locations

for

storing

system

specific

information (calibration data, serial numbers, system

ID information). A high-voltage requirement for

programming the nonvolatile locations on the HVC pin

ensures that these device settings are not accidentally

modified during normal system operation. Therefore, it

is recommended that the MTP memory should be only

programmed at the user’s factory.

The main functional blocks are:

• Power-on Reset/Brown-out Reset (POR/BOR)

• Device Memory

• Resistor Ladder

• Output Buffer/VOUT Operation

• SPI Serial Interface Module

4.1

Power-on Reset/Brown-out Reset

(POR/BOR)

The internal Power-on Reset (POR)/Brown-out Reset

(BOR) circuit monitors the power supply voltage (VDD)

during operation. This circuit ensures correct device

start-up at system power-up and power-down events.

The device’s RAM retention voltage (VRAM) is lower

than the POR/BOR voltage trip point (VPOR/VBOR).

The maximum VPOR/VBOR voltage is less than 1.8V.

The POR and BOR trip points are at the same voltage,

and the condition is determined by whether the VDD

voltage is rising or falling (see Figure 4-1). What occurs

is different depending on whether the reset is a POR or

BOR reset.

POR occurs as the voltage rises (typically from 0V),

while BOR occurs as the voltage falls (typically from

VDD(MIN) or higher).

When

VPOR/VBOR <VDD < 2.7V,

the

electrical

performance

may

not

meet

the

data

sheet

specifications. In this region, the device is capable of

reading and writing to its volatile memory if the proper

serial command is executed.

4.1.1

POWER-ON RESET

The Power-on Reset is the case where the device’s

VDD has power applied to it from the VSS voltage level.

As the device powers-up, the VOUT pin floats to an

unknown value. When the device’s VDD is above the

transistor threshold voltage of the device, the output

starts to be pulled low.

After the VDD is above the POR/BOR trip point

(VBOR/VPOR), the resistor network’s wiper is loaded

with the POR value. The POR value is either mid-scale

(MCP48CVBXX) or the user’s MTP programmed value

(MCP48CMBXX).

Volatile memory determines the analog output (VOUT)

pin voltage. After the device is powered-up, the user

can update the device memory.

Note:

In order to have the MCP48CMBXX

devices load the values from nonvolatile

memory locations at POR, they have to be

programmed at least once by the user;

otherwise, the loaded values will be the

default ones. After MTP programming, a

POR event is required to load the written

values from the nonvolatile memory.

MCP48CMB02 Datasheet(PDF) 43 Page - Microchip Technology

MCP48CMB02 Datasheet(HTML) 43 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL