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MCP48CMB02 Datasheet(PDF) 74 Page - Microchip Technology

Part # MCP48CMB02
Description  8/10/12-Bit Digital-to-Analog Converters, 1 LSb INL Single/Dual Voltage Outputs with SPI Interface
PDF  106 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

MCP48CMB02 Datasheet(HTML) 74 Page - Microchip Technology

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MCP48CXBXX
DS20006160A-page 74
 2019 Microchip Technology Inc.
7.6.2
CONTINUOUS READS
Continuous reads allows the devices memory to be
read quickly. Continuous reads are possible to all
memory locations. Read commands may only access
volatile memory locations during an MTP Write Cycle.
Figure 7-5 shows the sequence for three continuous
reads. The reads do not need to be to the same
memory address.
FIGURE 7-5:
Continuous Read Sequence.
12-bit data
10-bit data
8-bit data
SDI
AD
4
AD
3
AD
2
AD
1
AD
0
C
1
C
0
X
X
X
X
X
D
11
D
10
D
09
D
08
D
07
D
06
D
05
D
04
D
03
D
02
D
01
D
00
**
**
*
0
0
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
SDO
11
11
11
1
1
00
00
11
11
11
11
11
11 Valid(1)
11
11
11
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 Invalid(2)
Note 1: The Data bits depend on the resolution of the device: 12-bit = D11:D00,
10-bit = D09:D00, and 8-bit = D07:D00.
The unimplemented bits are output as ‘0’ and data are right justified for easy Host Controller
operation (no data manipulation after reading the register value).
2: If an Error Condition occurs (CMDERR = ‘0’), all the following SDO bits will be output as ‘0’
until the CMDERR condition is cleared (the CS pin is forced to the Inactive state).
3: This CMDERR bit will be forced to ‘0’, regardless if this Address + Command combination
is valid. This command will not be completed and requires the CS pin to return to VIH to clear
the CMDERR condition.
SDI
AD
4
AD
3
AD
2
AD
1
AD
0
C
1
C
0
X
X
X
X
X
D
11
D
10
D
09
D
08
D
07
D
06
D
05
D
04
D
03
D
02
D
01
D
00
**
**
*
0
0
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
SDO
11
11
11
1
1
00
00
11
11
11
11
11
11 Valid(1)
00
00
00
0 (3) 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 Invalid(2)
SDI
AD
4
AD
3
AD
2
AD
1
AD
0
C
1
C
0
X
X
X
X
X
D
11
D
10
D
09
D
08
D
07
D
06
D
05
D
04
D
03
D
02
D
01
D
00
**
**
*
0
0
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
SDO
11
11
11
1
1
00
00
11
11
11
11
11
11 Valid(1)
00
00
00
0 (3) 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 Invalid(2)



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