MCP48CMB02 datasheet(51/106 Pages) MICROCHIP

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 2019 Microchip Technology Inc.

DS20006160A-page 51

MCP48CXBXX

System Status register. Each DAC has one bit to

control the gain of the DAC and two Status bits.

GAIN CONTROL AND SYSTEM STATUS REGISTER (0Ah)

(VOLATILE)

U-0

R/W-n R/W-n R/C-1

U-0

Single

——

—(1)

POR MTPMA

—

——

Dual

—

POR MTPMA

—

bit 15

bit 0

Legend:

R = Readable bit

W = Writable bit

C = Clearable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

= Single-channel device

= Dual-channel device

Single

Dual

bit 15-9

bit 15-10 Unimplemented: Read as ‘0’

—

bit 9

G1: DAC1 Output Driver Gain control bits

1 = 2x Gain. Not applicable when VDD is used as VRL

(2)

0 = 1x Gain

bit 8

G0: DAC0 Output Driver Gain control bits

1 = 2x Gain. Not applicable when VDD is used as VRL

(2)

0 = 1x Gain

bit 7

POR: Power-on Reset (Brown-out Reset) Status bit

This bit indicates if a POR or BOR event has occurred since the last Read command of

this register. Reading this register clears the state of the POR Status bit.

1 = A POR (BOR) event occurred since the last read of this register. Reading this register clears

this bit.

0 = A POR (BOR) event has not occurred since the last read of this register.

bit 6

MTPMA: MTP Memory Access Status bit(3)

This bit indicates if the MTP Memory Access is occurring.

1 = An MTP Memory Access is currently occurring (during the POR MTP read cycle or an MTP

write cycle is occurring). Only serial commands addressing the volatile memory are allowed.

0 = An MTP memory Access is NOT currently occurring

bit 5-0

Unimplemented: Read as ‘0’

Note 1:

Unimplemented bit, read as ‘0’.

The DAC’s Gain bit is ignored, and the gain is forced to 1X (GX = “0”) when the DAC Voltage Reference is

selected as VDD (VRxB:VRxA = “00”).

For devices configured as volatile memory, this bit is read as ‘0’.

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