MCP48CMB02 datasheet(46/106 Pages) MICROCHIP

46 / 106 page

MCP48CXBXX

DS20006160A-page 46

 2019 Microchip Technology Inc.

It is recommended to keep high voltage on only during

the MTP Write command and programming cycle;

otherwise, the reliability of the device could be

affected.

4.2.3

UNIMPLEMENTED LOCATIONS

4.2.3.1

Unimplemented Register Bits

When issuing Read commands to a valid memory

location with unimplemented bits, the unimplemented

bits will be read as ‘0’.

4.2.4

UNIMPLEMENTED (RESERVED)

LOCATIONS

There are a number of unimplemented memory

locations that are reserved for future use. Normal

(Voltage) commands (Read or Write) to any

unimplemented memory address will result in a

Command Error condition (SPI Command Error -

CMDERR).

High-Voltage

commands

any

unimplemented configuration bit(s) will also result in a

Command Error condition.

4.2.5

POR/BOR OPERATION WITH

WIPERLOCK TECHNOLOGY

ENABLED

Regardless of the WiperLock Technology state, a POR

event will load the Volatile DACx Wiper register value

with the Nonvolatile DACx Wiper register value. Refer

to Section 4.1 “Power-on Reset/Brown-out Reset

(POR/BOR)” for further information.

TABLE 4-1:

MCP48CXBXX MEMORY MAP (16-BIT)

Function

00h Volatile DAC Wiper Register 0

Y Y

10h Nonvolatile DAC Wiper Register 0

Y Y

01h Volatile DAC Wiper Register 1

—Y

11h Nonvolatile DAC Wiper Register 1

—Y

02h Reserved

— —

12h Reserved

— —

03h Reserved

— —

13h Reserved

— —

04h Reserved

— —

14h Reserved

— —

05h Reserved

— —

15h Reserved

— —

06h Reserved

— —

16h Reserved

— —

07h Reserved

— —

17h Reserved

— —

08h Volatile VREF Register

Y Y

18h Nonvolatile VREF Register

Y Y

09h Volatile Power-Down Register

Y Y

19h Nonvolatile Power-Down

0Ah Volatile Gain and Status

1Ah NV Gain

Y Y

0Bh Reserved

— —

1Bh NV WiperLock™ Technology Register

Y Y

0Ch General Purpose MTP

(1)

1Ch General Purpose MTP

(1)

0Dh General Purpose MTP

(1)

1Dh General Purpose MTP

(1)

0Eh General Purpose MTP

(1)

1Eh General Purpose MTP

(1)

0Fh General Purpose MTP

(1)

1Fh General Purpose MTP

(1)

Legend:

Volatile Memory addresses

MTP Memory addresses

Memory locations not implemented on this device family

Note 1: On nonvolatile memory devices only (MCP48CMBXX)

MCP48CMB02 Datasheet(PDF) 46 Page - Microchip Technology

MCP48CMB02 Datasheet(HTML) 46 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL