28HS01GTAM03 datasheet(50/138 Pages) INFINEON

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Datasheet

50 of 138

002-18216 Rev. *W

2022-01-18

256Mb/512Mb/1Gb SEMPER™ Flash

Octal interface, 1.8V/3.0V

Features

The first 32-byte region (starting at address 0) provides the protection mechanism for the other 32-byte regions.

The sixteen lowest bytes of this region contain a 128-bit random number. The random number cannot be written

to, erased or programmed. The next four bytes (32 bits in total) of this region provide protection from

programming if set to '0' for the remaining 32-byte regions - one bit per 32-byte region. All other bytes are

reserved.

Note Attempting to Erase or Program the 128-bit random number will result in ERSERR or PRGERR respectively.

A hardware Reset is required to bring the device back to Standby mode.

4.5.3.1

SSR related registers and transactions

4.6

SafeBoot

SEMPER™ Flash memory devices contain an embedded microcontroller which is used to initialized the device,

manage embedded operations, and perform other advanced functionality. An initialization failure of this

embedded microcontroller or corruption of the nonvolatile configuration registers can render the flash device

unusable. Baring a catastrophic event, such as permanent corruption of the embedded microcontroller

firmware, it is possible to recover the device.

The SafeBoot feature allows Status Register polling to detect an embedded microcontroller initialization failure

or configuration register corruption through error signatures.

4.6.1

Microcontroller initialization failure detection

If the microcontroller embedded in the flash device fails to initialize, a hardware reset can recover the device,

unless it is a catastrophic failure. This hardware reset must be initiated by the Host controller. Upon detecting a

failed microcontroller initialization, the Flash device automatically reverts to its Default Boot mode (1S-1S-1S)

and provides a failure signature in its Status Register.

Table 22 shows the device’s Status Register bits upon detecting an initialization failure.

Table 21

SSR related registers and transactions

Related registers

Related SPI transactions

(see Table 75 on page 95)

Related octal transactions

(see Table 78 on page 99)

N/A

Program Secure Silicon Region (PRSSR_4_1)

Read Secure Silicon Region (RDSSR_4_0)

Table 22

Status register 1 power-on detection signature

Bit

Field name

Function

Detection

signature

STR1V[7]

RESRVD

Reserved for Future Use

STR1V[6]

PRGERR

Programming Error Status Flag

STR1V[5]

ERSERR

Erasing Error Status Flag

STR1V[4]

LBPROT[2:0]

Legacy Block Protection based memory Array size selection

Note: LBPRIT[2:0] can be anything from 000 to 111 based on Block Protection configu-

ration

STR1V[3]

STR1V[2]

STR1V[1]

WRPGEN

Write/Program Enable Status Flag

STR1V[0]

RDYBSY

Device Ready/Busy Status Flag

Table 23

Interface configuration upon detecting power-on failure[17]

Interface

Transactions supported

type

Address

(# of

bytes)

Frequency of operation

latency

(# of clock cycles)

Output

impedance

SPI

(1S-1S-1S)

Read Status Register 1

Read Any Register

Status

(Volatile Only)

Maximum (allowed for Read Status

transaction)

245

Note

17.For reading the Status Register, providing the nonvolatile Status Register address to Read Any Register transaction will produce

indeterminate results.

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