28HS01GTAM03 datasheet(11/138 Pages) INFINEON

11 / 138 page

Datasheet

11 of 138

002-18216 Rev. *W

2022-01-18

256Mb/512Mb/1Gb SEMPER™ Flash

Octal interface, 1.8V/3.0V

Interface overview

For SEMPER™ Flash Octal DDR mode operation, only clock Mode 0 is supported.

Figure 5

Octal DDR mode support

2.3

Transaction protocol

Transaction

• During the time that CS# is active (LOW), the clock signal (CK) is toggled while command information is first

transferred on the data (DQ) signals followed by address and data from the host to the flash device. The clock

continues to toggle during the transfer of read data from the flash device to the host or write data from the host

to the flash device. When the host has transferred the desired amount of data, the host drives the CS# inactive

(HIGH). The period during which CS# is active is called a transaction on the bus.

• While CS# is inactive, the CK is not required to toggle.

• The command transfer occurs at the beginning of every transaction. The address, latency cycles, and data

transfer phases are optional and their presence depends on the protocol mode or command transferred.

Transaction capture

• CK marks the transfer of each bit or group of bits between the host and memory. Command, address and write

data bits transfer occurs on CK rising edge in SDR transactions, or on every CK edge, in DDR transactions.

Note

• All attempts to read the flash memory array during a program or erase (embedded operations) are ignored. The

embedded operation will continue to execute without any effect. A very limited set of commands are accepted

during an embedded operation. These are discussed in Suspend and resume embedded operation on page

64.

Protocol terminology

• The number of DQ signals used during the transaction depends on the current protocol mode or command

transferred. The latency cycles do not use the DQ signals for information transfer. The protocol mode options

are described by the data rate and the DQ width (number of DQ signals) used during the command, address,

and data phases in the following format:

WR-WR-WR, where:

- The first WR is the command bit width and rate.

- The second WR is the address bit width and rate.

- The third WR is the data bit width and rate.

• The bit width value may be 1, or 8. R has a value of S for SDR or D for DDR. SDR has the same transfer value during

the rising and falling edge of a clock cycle. DDR can have different transfer values during the rising and falling

edges of each clock.

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