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28HS01GTAM03 Datasheet(PDF) 67 Page - Infineon Technologies AG |
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28HS01GTAM03 Datasheet(HTML) 67 Page - Infineon Technologies AG |
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67 / 138 page  Datasheet 67 of 138 002-18216 Rev. *W 2022-01-18 256Mb/512Mb/1Gb SEMPER™ Flash Octal interface, 1.8V/3.0V Features 4.13 Reset HL-T/HS-T devices support four types of reset mechanisms. • Hardware Reset (using RESET# input pin) •POR • CS# Signaling Reset • Software Reset 4.13.1 Hardware reset (using RESET# input pin) The RESET# input initiates the reset operation with a transition from logic HIGH to logic LOW for > tRP, and causes the device to perform the full reset process that is performed during POR. The hardware reset process requires a period of tRH to complete. See Table 85 for timing specifications. Figure 55 Hardware reset using RESET# input (reset pulse = tRP(Min)) Figure 56 Hardware reset using RESET# input (reset pulse > (tRP + tRH)) Figure 57 Hardware reset using RESET# input (back to back hardware reset) |
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