28HS01GTAM03 datasheet(68/138 Pages) INFINEON

68 / 138 page

Datasheet

68 of 138

002-18216 Rev. *W

2022-01-18

256Mb/512Mb/1Gb SEMPER™ Flash

Octal interface, 1.8V/3.0V

Features

4.13.2

Power-on reset (POR)

The device executes a POR process until a time delay of tPU has elapsed after the moment that VCC rises above

the minimum VCC threshold (see Figure 58 and Figure 59). The device must not be selected during power-up

(tPU). Therefore,CS#mustrisewithVCC. No commandsmaybesentto the deviceuntiltheendoftPU.SeeTable 85

for timing specifications.

RESET# is ignored during POR. If RESET# is LOW during POR and remains LOW through and beyond the end of

tPU, CS# must remain HIGH until tRS after RESET# returns HIGH.

Figure 58

Reset LOW at the end of POR

Figure 59

Reset HIGH at the end of POR

4.13.3

CS# signaling reset

The CS# Signaling Reset requires CS# and DQ0 signals. This reset method defines a signaling protocol, using

existing signals, to initiate an SPI Flash hardware reset, independent of the device operating mode or number of

package pins.

The Signaling Protocol is shown in Figure 60. See Table 85 for timing specifications. The CS# signaling reset

steps are as follows:

• CS# is driven active LOW.

• CK remains stable in either HIGH or LOW state.

• CS# and DQ0 are both driven LOW.

• CS# is driven HIGH (inactive).

• Repeat the above four steps, each time alternating the state of DQ0 for a total of four times.

• Reset occurs after the fourth CS# cycle completes and it goes HIGH (inactive).

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