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28HS01GTAM03 Datasheet(PDF) 20 Page - Infineon Technologies AG |
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28HS01GTAM03 Datasheet(HTML) 20 Page - Infineon Technologies AG |
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20 / 138 page  Datasheet 20 of 138 002-18216 Rev. *W 2022-01-18 256Mb/512Mb/1Gb SEMPER™ Flash Octal interface, 1.8V/3.0V Interface overview Figure 27 Octal SDR read transaction with command and address input (output latency) Figure 28 Octal DDR read transaction with command and address input (output latency)[4, 5] Figure 29 Octal DDR single byte read transaction with command and address input (output latency)[6] Command CK CS# DQ[7:0] DS Latency Cycles CMD [7:0] CMD [7:0] ADDR [31:24] MSb LSb DOUT A [7:0] DOUT A+n [7:0] Read Data ADDR [7:0] MSB LSB Address Pre Drive MSb LSb Command CK CS# DQ[7:0] DS Latency Cycles CMD [7:0] CMD [7:0] ADDR [31:24] MSb LSb DOUT A [7:0] DOUT A+n [7:0] Read Data ADDR [7:0] MSB LSB Address Pre Drive MSb LSb 2.5 Cycles Command CK CS# DQ[7:0] DS Latency Cycles CMD [7:0] CMD [7:0] ADDR [31:24] MSb LSb DOUT A [7:0] DOUT A+n [7:0] Read Data ADDR [7:0] MSB LSB Address Pre Drive MSb LSb 2.5 Cycles Notes 4. The LSb of the address always be zero in any Octal DDR transactions with the address input. 5. Read Interface CRC Transaction is supported with Octal DDR only. Command CK CS# DQ[7:0] DS CMD [7:0] CMD [7:0] ADDR [31:24] MSb LSb Read Data ADDR [23:16] ADDR [15:8] Pre Drive DOUT A [7:0] DOUT A+1 [7:0] DOUT A+n [7:0] MSb LSb ADDR [7:0] Command CK CS# DQ[7:0] DS CMD [7:0] CMD [7:0] ADDR [31:24] MSb LSb Read Data ADDR [23:16] ADDR [15:8] Pre Drive DOUT A [7:0] DOUT A+1 [7:0] DOUT A+n [7:0] MSb LSb ADDR [7:0] 2.5 Cycles Command CK CS# DQ[7:0] DS CMD [7:0] CMD [7:0] ADDR [31:24] MSb LSb Read Data ADDR [23:16] ADDR [15:8] Pre Drive DOUT A [7:0] DOUT A+1 [7:0] DOUT A+n [7:0] MSb LSb ADDR [7:0] 2.5 Cycles Command CK CS# DQ[7:0] DS Latency Cycles CMD [7:0] CMD [7:0] ADDR [31:24] MSb LSb Read Data ADDR [7:0] MSB LSB Address Pre Drive DOUT [7:0] Undefined MSb LSb Command CK CS# DQ[7:0] DS Latency Cycles CMD [7:0] CMD [7:0] ADDR [31:24] MSb LSb Read Data ADDR [7:0] MSB LSB Address Pre Drive DOUT [7:0] Undefined MSb LSb Command CK CS# DQ[7:0] DS Latency Cycles CMD [7:0] CMD [7:0] ADDR [31:24] MSb LSb Read Data ADDR [7:0] MSB LSB Address Pre Drive DOUT [7:0] Undefined MSb LSb |
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