28HS01GTAM03 datasheet(119/138 Pages) INFINEON

119 / 138 page

Datasheet

119 of 138

002-18216 Rev. *W

2022-01-18

256Mb/512Mb/1Gb SEMPER™ Flash

Octal interface, 1.8V/3.0V

Device identification

124h

JEDEC Basic Flash

Parameter DWORD-10

23h

Bits 31:30 = Erase type 4 Erase, Typical time units (00b: 1 ms, 01b: 16 ms, 10b: 128 ms,

11b: 1 s) = 128 ms = 10b

Bits 29:25 = Erase type 4 Erase, Typical time count = 00101b (typ erase time = count

+1 * units = 6 * 128 ms = 768 ms)

Bits 24:23 = Erase type 3 Erase, Typical time units (00b: 1 ms, 01b: 16 ms, 10b: 128 ms,

11b: 1 s) = 1S = 11b (RFU)

Bits 22:18 = Erase type 3 Erase, Typical time count = 11111b (RFU)

Bits 17:16 = Erase type 2 Erase, Typical time units (00b: 1 ms, 01b: 16 ms, 10b: 128 ms,

11b: 1 s) = 1S = 11b (RFU)

Bits 15:11 = Erase type 2 Erase, Typical time count = 11111b (RFU)

Bits 10:9 = Erase type 1 Erase, Typical time units (00b: 1 ms, 01b: 16 ms, 10b: 128 ms,

11b: 1 s) = 16ms = 01b

Bits 8:4 = Erase type 1 Erase, Typical time count = 00010b (typ erase time = count +1

* units = 3 * 16 ms = 48 ms)

Bits 3:0 = Count = (Max Erase time / (2 * Typical Erase time))- 1 = 0011b

125h

FAh

126h

FFh

127h

8Bh

128h

JEDEC Basic Flash

Parameter DWORD-11

82h

Bits 31 = Reserved = 1b

Bits 30:29 = Chip Erase Typical time units (00b: 16 ms, 01b: 256 ms, 10b: 4 s, 11b: 64

s) = 11b (256M, 512M, and 1G)

Bits 28:24 = Chip Erase Typical time count = 00001b (256M), 00011b (512M), and

00110b (1G)

Bits 23:19 = Byte Program Typical Time, additional byte = 11111b

Bits 18:14 = Byte Program Typical Time, first byte = 11111b

Bits 13 = Page Program Typical Time unit (0: 8 μs, 1: 64 μs) = 64 μs = 1b

Bits 12:8 = Page Program Typical Time Count = 00111 (typ Program time = count +1 *

units = 8 * 64 μs = 512 μs)

Bits 7:4 = Page Size (256B) = 2^N bytes = 1000h

Bits 3:0 = Count = [Max page program time / (2 * Typical page program time)] - 1 =

0010b

129h

E7h

12Ah

FFh

12Bh

E1h for 256M

E3h for 512M

E6h for 1G

12Ch

JEDEC Basic Flash

Parameter DWORD-12

ECh

Bit 31 = Suspend and Resume supported = 0b

Bits 30:29 = Suspend in-progress erase max latency units (00b: 128ns, 01b: 1μs, 10b:

8μs, 11b: 64μs) = 8 μs = 10b

Bits 28:24 = Suspend in-progress erase max latency count = 01001b, max erase

suspend latency = count +1 * units

= 10 * 8 μs = 80 μs

Bits 23:20 = Erase resume to suspend interval count = 0001b, interval = count +1 * 64

μs = 2 * 64 μs = 128 μs

Bits 19:18 = Suspend in-progress program max latency units (00b: 128ns, 01b: 1μs,

10b: 8μs, 11b: 64μs)

= 8 μs = 10b

Bits 17:13 = Suspend in-progress program max latency count = 01001b, max program

suspend latency = count +1 * units

= 10 * 8 μs = 80 μs

Bits 12:9 = Program resume to suspend interval count = 0001b, interval = count +1 *

64 μs = 2 * 64 μs = 128 μs

Bit 8 = Reserved = 1b

Bits 7:4 = Prohibited operations during erase suspend

= xxx0b: May not initiate a new erase anywhere (erase nesting not permitted)

+ xx1xb: May not initiate a page program in the erase suspended sector size

+ x1xxb: May not initiate a read in the erase suspended sector size

+ 1xxxb: The erase and program restrictions in bits 5:4 are sufficient

= 1110b

Bits 3:0 = Prohibited Operations During Program Suspend

= xxx0b: May not initiate a new erase anywhere (erase nesting not permitted)

+ xx0xb: May not initiate a new page program anywhere (program nesting not

permitted)

+ x1xxb: May not initiate a read in the program suspended page size

+ 1xxxb: The erase and program restrictions in bits 1:0 are sufficient

= 1100b

12Dh

23h

12Eh

19h

12Fh

49h

130h

JEDEC Basic Flash

Parameter DWORD-13

7Ah

Bits 7:0 = Program Resume Instruction = 7Ah (1S-1S-1S)

131h

B0h

Bits 15:8 = Program Suspend Instruction = B0h

132h

7Ah

Bits 23:16 = Erase Resume Instruction = 7Ah (1S-1S-1S)

133h

B0h

Bits 31:24 = Erase Suspend Instruction = B0h

134h

JEDEC Basic Flash

Parameter DWORD-14

F7h

Bits 7:4 = RFU = Fh

Bit 3:2 = Status Register Polling Device Busy = 01b: Legacy status polling supported =

Use legacy polling by reading the Status Register with 05h instruction and checking

WIP bit[0] (0 = ready; 1 = busy).

Bits 1:0 = RFU = 11b

135h

66h

Bit 31 = DPD Supported = supported = 0

Bits 30:23 = Enter DPD Instruction = B9h

Bits 22:15 = Exit DPD Instruction not supported = 00h

Bits 14:13 = Exit DPD to next operation delay units = (00b: 128 ns, 01b: 1 μs, 10b: 8 μs,

11b: 64 μs) = 64 μs = 11b

Bits 12:8 = Exit DPD to next operation delay count = 00110, Exit DPD to next operation

delay

= (count+1) * units = (6 + 1) * 64 μs = 448 μs

136h

80h

137h

5Ch

Table 87

JEDEC SFDP Rev D parameter table (Continued)

SFDP byte address

SFDP DWORD name

Data

Description

28HS01GTAM03 Datasheet(PDF) 119 Page - Infineon Technologies AG

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