28HS01GTAM03 datasheet(126/138 Pages) INFINEON

126 / 138 page

Datasheet

126 of 138

002-18216 Rev. *W

2022-01-18

256Mb/512Mb/1Gb SEMPER™ Flash

Octal interface, 1.8V/3.0V

Device identification

1C4h

Status, Control and

Configuration Register

Map DWORD-23

71h

Bits 7:0 = Command used for write access = 71h

1C5h

65h

Bits 15:8 = Command used for read access = 65h

1C6h

06h

Address of register where DTR Octal Mode Enable nonvolatile bit is located = 06h

(Configuration Reg - 5 nonvolatile)

1C7h

91h

Bit 31 = DTR Octal Mode Enable nonvolatile bit supported = 1b

Bits 30 = DTR Octal Mode Enable nonvolatile bit polarity positive (DSTR Octal Mode

Enable = 1 indicates DTR Octal Mode is enabled) = 0b

Bit 29 = No OTP Bit = 0b

Bits 28 = Bit is set/cleared by commands using address = 1b

Bit 27 = Not supported = 0b

Bits 26:24 = Bit location of DTR Octal Mode Enable bit in register = bit [1] = 001b

1C8h

Status, Control and

Configuration Register

Map DWORD-24

00h

Not Supported

1C9h

00h

1CAh

FFh

1CBh

00h

1CCh

Status, Control and

Configuration Register

Map DWORD-25

00h

Not Supported

1CDh

00h

1CEh

FFh

1CFh

00h

1D0h

Status, Control and

Configuration Register

Map DWORD-26

71h

Bits 7:0 = Command used for write access = 71h

1D1h

65h

Bits 15:8 = Command used for read access = 65h

1D2h

05h

Address of register where Output Driver Strength volatile bits are located = 800005h

(Configuration Reg - 4 Volatile)

1D3h

D5h

Bits 31: 30 = Number of physical bits used to set Output Driver Strength = 3 bits = 11b

Bit 29 = Reserved = 0b

Bits 28 = Bit is set/cleared by commands using address = 1b

Bit 27 = Not Supported = 0b

Bits 26:24 = Bit location of Least Significant Output Driver Strength bit in register = bit

[5] = 101b

1D4h

Status, Control and

Configuration Register

Map DWORD-27

71h

Bits 7:0 = Command used for write access = 71h

1D5h

65h

Bits 15:8 = Command used for read access = 65h

1D6h

05h

Address of register where Output Driver Strength nonvolatile bits are located = 05h

(Configuration Reg - 4 non- volatile)

1D7h

D5h

Bits 31: 30 = Number of physical bits used to set Output Driver Strength = 3 bits = 11b

Bit 29 = Reserved = 0b

Bits 28 = Bit is set/cleared by commands using address = 1b

Bit 27 = Not Supported = 0b

Bits 26:24 = Bit location of Least Significant Output Driver Strength bit in register = bit

[5] = 101b

1D8h

Status, Control and

Configuration Register

Map DWORD-28

00h

Bit 7:0 = Reserved = 00h

1D9h

00h

Bit 15:8 = Reserved = 00h

1DAh

A0h

Bits 31:29 = Bit pattern to support Driver type 0 = 45 Ohms = 000b

Bits 28:26 = Bit pattern to support Driver type 1 = 30 Ohm = 101b

Bits 25:23 = Bit pattern to support Driver type 2 = 60 Ohm = 011b

Bits 22:20 = Bit pattern to support Driver type 3 = 90 Ohm = 010b

Bits 19:17 = Bit pattern to support Driver type 4 = Not supported = 000b

Bit 16 = Reserved = 0b

1DBh

15h

1DCh

Command Sequences

to Change to Octal DDR

(8D-8D-8D) mode

DWORD -1

00h

Bits 7:0 = Byte 3 of first command sequence

1DDh

00h

Bits 15:8 = Byte 2 of first command sequence

1DEh

06h

Bits 23:16 = Byte 1 of first command sequence

1DFh

01h

Bits 31:24 = Length of first command sequence = 1 byte

1E0h

Command Sequences

to Change to Octal DDR

(8D-8D-8D) mode

DWORD -2

00h

Bits 7:0 = Byte 7 of first command sequence

1E1h

00h

Bits 15:8 = Byte 6 of first command sequence

1E2h

00h

Bits 23:16 = Byte 5 of first command sequence

1E3h

00h

Bits 31:24 = Byte 4 of first command sequence

Table 87

JEDEC SFDP Rev D parameter table (Continued)

SFDP byte address

SFDP DWORD name

Data

Description

28HS01GTAM03 Datasheet(PDF) 126 Page - Infineon Technologies AG

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