AD9161BBCZ datasheet(48/144 Pages) AD

48 / 144 page

AD9161/AD9162

Data Sheet

Rev. D | Page 48 of 144

PHY 0, PHY 1, PHY 6, and PHY 7. Register 0x2AE controls

autocalibration for PHY 2, PHY 3, PHY 4, and PHY 5.

The PHY termination autocalibration routine is as shown in

Table 18.

Table 18. PHY Termination Autocalibration Routine

Address

Value

Description

0x2A7

0x01

Autotune PHY 0, PHY 1, PHY 6, and

PHY 7 terminations

0x2AE

0x01

Autotune PHY 2, PHY 3, PHY 4, and

PHY 5 terminations

The input termination voltage of the DAC is sourced externally

via the VTT_1P2 pins (M3 and M 13 on the 8 mm × 8 mm

BGA package, or K3 and K13 on the 11 mm × 11 mm BGA

package). Set VTT, the termination voltage, by connecting it to

VDD_1P2. It is recommended that the JESD204B inputs be ac-

coupled to the JESD204B transmit device using 100 nF capacitors.

The calibration code of the termination can be read from

Bits[3:0] in Register 0x2AC (PHY 0, PHY 1, PHY 6, PHY 7)

and Register 0x2B3 (PHY 2, PHY 3, PHY 4, PHY 5). If needed,

the termination values can be adjusted or set using several

registers. The TERM_BLKx_CTRLREG1 registers (Register 0x2A8

and Register 0x2AF), can override the autocalibrated value. When

set to 0xXXX0XXXX, the termination block autocalibrates,

which is the normal, default setting. When set to 0xXXX1XXXX,

the autocalibration value is overwritten with the value in Bits[3:1]

of Register 0x2A8 and Register 0x2AF. Individual offsets from the

autocalibration value for each lane can be programmed in Bits[3:0]

of Register 0x2BB to Register 0x2C2. The value is a signed magni-

tude, with Bit 3 as the sign bit. The total range of the termination

resistor value is about 94 Ω to 120 Ω, with approximately 3.5%

increments across the range (for example, smaller steps at the

bottom of the range than at the top).

Receiver Eye Mask

The AD9161/AD9162 comply with the JESD204B specification

regarding the receiver eye mask and is capable of capturing data

that complies with this mask. Figure 145 shows the receiver eye

mask normalized to the data rate interval with a 600 mV VTT

swing. See the JESD204B specification for more information

regarding the eye mask and permitted receiver eye opening.

525

–55

–525

0.5

1.00

0.35

0.65

TIME (UI)

LV-OIF-11G-SR RECEIVER EYE MASK

Figure 145. Receiver Eye Mask for 600 mV VTT Swing

Clock Relationships

The following clocks rates are used throughout the rest of the

JESD204B section. The relationship between any of the clocks

can be derived from the following equations:

DataRate = (DACRate)/(InterpolationFactor)

LaneRate = (20 × DataRate × M)/L

ByteRate = LaneRate/10

This relationship comes from 8-bit/10-bit encoding, where each

byte is represented by 10 bits.

PCLK Rate = ByteRate/4

The processing clock is used for a quad-byte decoder.

FrameRate = ByteRate/F

where F is defined as octets per frame per lane.

PCLK Factor = FrameRate/PCLK Rate = 4/F

where:

M is the JESD204B parameter for converters per link.

L is the JESD204B parameter for lanes per link.

F is the JESD204B parameter for octets per frame per lane.

SERDES PLL

Functional Overview of the SERDES PLL

The independent SERDES PLL uses integer N techniques to

achieve clock synthesis. The entire SERDES PLL is integrated

on chip, including the VCO and the loop filter. The SERDES

PLL VCO operates over the range of 6 GHz to 12.5 GHz.

In the SERDES PLL, a VCO divider block divides the VCO

clock by 2 to generate a 3 GHz to 6.25 GHz quadrature clock for

the deserializer cores. This clock is the input to the clock and

data recovery block that is described in the Clock and Data

Recovery section.

The reference clock to the SERDES PLL is always running at a

frequency, fREF, which is equal to 1/40 of the lane rate (PCLK Rate).

This clock is divided by a DivFactor value (set by SERDES_PLL_

DIV_FACTOR) to deliver a clock to the phase frequency detector

(PFD) block that is between 35 MHz and 80 MHz. Table 19

includes the respective SERDES_PLL_DIV_FACTOR register

settings for each of the desired PLL_REF_CLK_RATE options

available.

Table 19. SERDES PLL Divider Settings

Lane Rate

(Gbps)

PLL_REF_CLK_RATE,

SERDES_PLL_DIV_FAC

TOR Register 0x289,

Bits[1:0]

0.750 to 1.5625

0b01 = 2×

0b10 = ÷1

1.5 to 3.125

0b00 = 1×

0b10 = ÷1

3 to 6.25

0b00 = 1×

0b01 = ÷2

6 to 12.5

0b00 = 1×

0b00 = ÷4

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