AD9161BBCZ datasheet(82/144 Pages) AD

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AD9161/AD9162

Data Sheet

Rev. D | Page 82 of 82

START-UP SEQUENCE

A number of steps is required to program the AD9161/AD9162

to the proper operating state after the device is powered up. This

sequence is divided into several steps, and is listed in Table 42,

Table 43, and Table 44, along with an explanation of the purpose of

each step. Private registers are reserved but must be written for

proper operation. Blank cells in Table 42 to Table 44 mean that

the value depends on the result as described in the description

column.

The AD9161/AD9162 are calibrated at the factory as part of the

automatic test program. The configure DAC start-up sequence

loads the factory calibration coefficients, as well as configures

some parameters that optimize the performance of the DAC

and the DAC clock DLL (see Table 42). Run this sequence

whenever the DAC is powered down or reset.

The configure JESD204B sequence configures the SERDES

block and then brings up the links (see Table 43). First, run the

configure DAC start-up sequence, then run the configure

JESD204B sequence.

Follow the configure NCO sequence if using the NCO (see

Table 44). Note that the NCO can be used in NCO only mode

or in conjunction with synthesized data from the SERDES data

interface. Only one mode can be used at a time and this mode is

selected in the second step in Table 44. The configure DAC

start-up sequence is run first, then the configure NCO sequence.

Table 42. Configure DAC Start-Up Sequence After Power-Up

R/W

Value

Description

0x000

0x18

Configure the device for 4-wire serial port operation (optional: leave at the default of 3-wire SPI)

0x0D2

0x52

Reset internal calibration registers (private)

0x0D2

0xD2

Clear the reset bit for the internal calibration registers (private)

0x606

0x02

Configure the nonvolatile random access memory (NVRAM) (private)

0x607

0x00

Configure the NVRAM (private)

0x604

0x01

Load the NVRAM. Loads factory calibration factors from the NVRAM. (private)1

0x003, 0x004, 0x005,

0x006

N/A2

(Optional) read CHIP_TYPE, PROD_ID[15:0], PROD_GRADE, and DEV_REVISION from Register 0x003,

0x604, Bit 1

0b1

(Optional) read the boot loader pass bit in Register 0x604, Bit 1 = 0b1 to indicate a successful boot

load

0x058

0x03

Enable the band gap reference (private)

0x090

0x1E

Power up the DAC clock DLL

0x080

0x00

Enable the clock receiver

0x040

0x00

Enable the DAC bias circuits

0x020

0x0F

Optional. Enable the interrupts

0x09E

0x85

Configure DAC analog parameters (private)

0x091

0xE9

Enable the DAC clock DLL

0x092, Bit 0

0b1

Check DLL_STATUS; set Register 0x092, Bit 0 = 1 to indicate the DAC clock DLL is locked to the DAC

clock input

0x0E8

0x20

Enable calibration factors (private)

0x152, Bits[1:0]

Configure the DAC decode mode (0b00 = NRZ, 0b01 = mix mode, or 0b10 = RZ)

1 After the NVRAM is loaded, the readback values of registers 0x004 and 0x005 change to 0x004 = 0x62 for the AD9162, 0x004 = 0x61 for the AD9161, 0x005 = 0x91.

2 N/A means not applicable.

Table 43. Configure JESD204B Start-Up Sequence

R/W

Value

Description

0x300

0x00

Ensure the SERDES links are disabled before configuring them.

0x4B8

0xFF

Enable JESD204B interrupts.

0x4B9

0x01

Enable JESD204B interrupts.

0x480

0x38

Enable SERDES error counters.

0x481

0x38

Enable SERDES error counters.

0x482

0x38

Enable SERDES error counters.

0x483

0x38

Enable SERDES error counters.

0x484

0x38

Enable SERDES error counters.

0x485

0x38

Enable SERDES error counters.

0x486

0x38

Enable SERDES error counters.

0x487

0x38

Enable SERDES error counters.

0x110

Configure number of lanes (Bits[7:4]) and interpolation rate (Bits[3:0]).

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