AD9161BBCZ datasheet(75/144 Pages) AD

75 / 144 page

Data Sheet

AD9161/AD9162

Rev. D | Page 75 of 75

Insertion Loss

The JESD204B specification limits the amount of insertion loss

allowed in the transmission channel (see Figure 147). The

AD9161/AD9162 equalization circuitry allows significantly more

loss in the channel than is required by the JESD204B specification.

It is still important that the designer of the PCB minimize the

amount of insertion loss by adhering to the following

guidelines:



Keep the differential traces short by placing the

AD9161/AD9162 as near the transmitting logic device as

possible and routing the trace as directly as possible between

the devices.



Route the differential pairs on a single plane using a solid

ground plane as a reference. It is recommended to route the

SERDES lanes on the same layer as the AD9161/AD9162 to

avoid vias being used in the SERDES lanes.



Use a PCB material with a low dielectric constant (<4) to

minimize loss, if possible.

When choosing between the stripline and microstrip techniques,

keep in mind the following considerations: stripline has less loss

(see Figure 148 and Figure 149) and emits less EMI, but

requires the use of vias that can add complexity to the task of

controlling the impedance; whereas microstrip is easier to

implement (if the component placement and density allow

routing on the top layer) and eases the task of controlling the

impedance.

If using the top layer of the PCB is problematic or the advantages

of stripline are desirable, follow these recommendations:



Minimize the number of vias.



If possible, use blind vias to eliminate via stub effects and

use microvias to minimize via inductance.



If using standard vias, use the maximum via length to

minimize the stub size. For example, on an 8-layer board,

use Layer 7 for the stripline pair (see Figure 176).



For each via pair, place a pair of ground vias adjacent to them

to minimize the impedance discontinuity (see Figure 176).

LAYER 1

LAYER 2

LAYER 3

LAYER 4

LAYER 5

LAYER 6

LAYER 7

LAYER 8

MINIMIZE STUB EFFECT

GND

DIFF–

DIFF+

ADD GROUND VIAS

STANDARD VIA

Figure 176. Minimizing Stub Effect and Adding Ground Vias for Differential

Stripline Traces

Return Loss

The JESD204B specification limits the amount of return loss

allowed in a converter device and a logic device, but does not

specify return loss for the channel. However, every effort must

be made to maintain a continuous impedance on the transmis-

sion line between the transmitting logic device and the AD9161/

AD9162. Minimizing the use of vias, or eliminating them all

together, reduces one of the primary sources for impedance

mismatches on a transmission line (see the Insertion Loss section).

Maintain a solid reference beneath (for microstrip) or above

and below (for stripline) the differential traces to ensure continuity

in the impedance of the transmission line. If the stripline tech-

nique is used, follow the guidelines listed in the Insertion Loss

section to minimize impedance mismatches and stub effects.

Another primary source for impedance mismatch is at either

end of the transmission line, where care must be taken to match

the impedance of the termination to that of the transmission

line. The AD9161/AD9162 handle this internally with a cali-

brated termination scheme for the receiving end of the line. See

the Interface Power-Up and Input Termination section for details

on this circuit and the calibration routine.

Signal Skew

There are many sources for signal skew, but the two sources to

consider when laying out a PCB are interconnect skew within a

single JESD204B link and skew between multiple JESD204B

links. In each case, keeping the channel lengths matched to

within 12.5 mm is adequate for operating the JESD204B link at

speeds of up to 12.5 Gbps. This amount of channel length

match is equivalent to about 85% UI on the AD9161/AD9162

evaluation board. Managing the interconnect skew within a

single link is fairly straightforward. Managing multiple links

across multiple devices is more complex. However, follow the

12.5 mm guideline for length matching. The AD9161/AD9162

can handle more skew than the 85% UI due to the 6 PCLK

buffer in the JESD204B receiver, but matching the channel

lengths as close as possible is still recommended.

Topology

Structure the differential SERDINx± pairs to achieve 50 Ω to

ground for each half of the pair. Stripline vs. microstrip trade-

offs are described in the Insertion Loss section. In either case, it

is important to keep these transmission lines separated from

potential noise sources such as high speed digital signals and

noisy supplies. If using stripline differential traces, route them

using a coplanar method, with both traces on the same layer.

Although this method does not offer more noise immunity than

the broadside routing method (traces routed on adjacent

layers), it is easier to route and manufacture so that the

impedance continuity is maintained. An illustration of

broadside vs. coplanar is shown in Figure 177.

Tx DIFF A

DIFF A

DIFF B

ACTIVE

Tx DIFF B

Tx ACTIVE

BROADSIDE DIFFERENTIAL Tx LINES

COPLANAR DIFFERENTIAL Tx LINES

Figure 177. Broadside vs. Coplanar Differential Stripline Routing Techniques

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