AD9161BBCZ datasheet(63/144 Pages) AD

63 / 144 page

Data Sheet

AD9161/AD9162

Rev. D | Page 63 of 144

Check for Error Count Over Threshold

To check for the error count over threshold, follow these steps:

1. Define the error counter threshold. The error counter

threshold can be set to a user defined value in Register

0x47C, or left to the default value of 0xFF. When the error

threshold is reached, an IRQ is generated or SYNCOUT±

is asserted or both, depending on the mask register

settings. This one error threshold is used for all three types

of errors (UEK, NIT, and BDE).

2. Set the SYNC_ASSERT_MASK bits. The SYNCOUT±

assertion behavior is set in Register 0x47D, Bits[2:0]. By

default, when any error counter of any lane is equal to the

threshold, it asserts SYNCOUT± (Register 0x47D, Bits[2:0]

= 0b111).

3. Read the error count reached indicator. Each error counter

has a terminal count reached indicator, per lane. This

indicator is set to 1 when the terminal count of an error

counter for a particular lane has been reached. These status

bits are located in Register 0x490, Bits[2:0] to Register

0x497, Bits[2:0]. These registers also indicate whether a

particular lane is active by setting Bit 3 = 0b1.

Error Counter and IRQ Control

For error counter and IRQ control, follow these steps:

1. Enable the interrupts. Enable the JESD204B interrupts. The

interrupts for the UEK, NIT, and BDE error counters are in

monitor when bringing up the link, such as lane deskewing,

initial lane sync, good check sum, frame sync, code group sync

(Register 0x4B8, Bits[4:0], and configuration mismatch

(Register 0x4B9, Bit 0). These bits are off by default but can

be enabled by writing 0b1 to the corresponding bit.

a) Read the JESD204B interrupt status. The interrupt

status bits are in Register 0x4BA, Bits[7:0] and

corresponding to the enable bit position.

2. It is recommended to enable all interrupts that are planned

to be used prior to bringing up the JESD204B link. When

the link is up, the interrupts can be reset and then used to

monitor the link status.

Monitoring Errors via SYNCOUT±

When one or more disparity, NIT, or unexpected control

character errors occur, the error is reported on the SYNCOUT±

pin as per Section 7.6 of the JESD204B specification. The

JESD204B specification states that the SYNCOUT± signal is

asserted for exactly two frame periods when an error occurs. For

the AD9161/AD9162, the width of theSYNCOUT± pulse can be

programmed to ½, 1, or 2 PCLK cycles. The settings to achieve a

SYNCOUT± pulse of two frame clock cycles are given in Table 32.

Table 32. Setting SYNCOUT± Error Pulse Duration

These register settings assert the SYNCOUT± signal for two frame clock cycle

pulse widths.

Unexpected Control Character, NIT, Disparity IRQs

For UEK character, NIT, and disparity errors, error count over

the threshold events are available as IRQ events. Enable these

events by writing to Register 0x4B8, Bits[7:5]. The IRQ event

status can be read at Register 0x4BA, Bits[7:5] after the IRQs are

enabled.

See the Error Counter and IRQ Control section for information

on resetting the IRQ. See the Interrupt Request Operation

section for more information on IRQs.

Errors Requiring Reinitializing

A link reinitialization automatically occurs when four invalid

disparity characters are received as per Section 7.1 of the

JESD204B specification. When a link reinitialization occurs, the

resync request is five frames and nine octets long.

The user can optionally reinitialize the link when the error

count for disparity errors, NIT errors, or UEK character errors

reaches a programmable error threshold. The process to enable

the reinitialization feature for certain error types is as follows:

1. Choose and enable which errors to monitor by selecting

them in Register 0x480, Bits[5:3] to Register 0x487,

Bits[5:3]. UEK, BDE, and NIT error monitoring can be

selected for each lane by writing a 1 to the appropriate bit,

as described in Table 46. These are enabled by default.

2. Enable the sync assertion mask for each type of error by

writing to SYNC_ASSERT_MASK (Register 0x47D,

Bits[2:0]) according to Table 33.

3. Program the desired error counter threshold into

ERRORTHRES (Register 0x47C).

4. For each error type enabled in the SYNC_ASSERT_MASK

programmed threshold, SYNCOUT± falls, issuing a sync

request. Note that all error counts are reset when a link

reinitialization occurs. The IRQ does not reset and must be

reset manually.

PCLK Factor

(Frames/PCLK)

SYNC_ERR_DUR (Register 0x312,

Bits[7:4]) Setting1

0 (default)

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