AD9161BBCZ datasheet(94/144 Pages) AD

94 / 144 page

AD9161/AD9162

Data Sheet

Rev. D | Page 94 of 144

Hex.

Addr. Name

Bits Bit Name

Settings

Description

Reset

Access

SPI_DATAPATH_PRE

SPI control of the data at the

input of the datapath.

0x1

R/W

0 Disable or zero the data feeding

into the datapath.

1 Use the data from the JESD204B

lanes to drive into the datapath.

[5:4] RESERVED

Reserved.

0x0

TXEN_NCO_RESET

Allows TX_ENABLE to control

the DDS NCO reset.

0x0

R/W

0 Use the SPI (HOPF_MODE SPI

bits) to control the DDS NCO

reset.

1 Use the TX_ENABLE pin to

control the DDS NCO reset.

TXEN_DATAPATH_POST

Allows TX_ENABLE to control

the data at the output of the

datapath.

0x0

R/W

0 Use the SPI (Bit

SPI_DATAPATH_ POST) for

control.

1 Use the TX_ENABLE pin for

control.

TXEN_DATAPATH_PRE

Allows TX_ENABLE to control

the data at the input of the

datapath.

0x0

R/W

0 Use the SPI (Bit

SPI_DATAPATH_ PRE) for

control.

1 Use the TX_ENABLE pin for

control.

TXEN_DAC_FSC

Allows TX_ENABLE to control

the DAC full-scale current.

0x0

R/W

0 Use the SPI register ANA_FSC0

and ANA_FSC1 for control.

1 Use the TX_ENABLE pin for

control.

0x040 ANA_DAC_BIAS_PD

[7:2] RESERVED

Reserved.

0x0

ANA_DAC_BIAS_PD1

Powers down the DAC core bias

circuits. A 1 powers down the

DAC core bias circuits.

0x1

R/W

ANA_DAC_BIAS_PD0

Powers down the DAC core bias

circuits. A 1 powers down the

DAC core bias circuits.

0x1

R/W

0x041 ANA_FSC0

[7:2] RESERVED

Reserved.

0x0

[1:0] ANA_FULL_SCALE_CURRENT[1:0]

DAC full-scale current. Analog

full-scale current adjustment.

0x3

R/W

0x042 ANA_FSC1

[7:0] ANA_FULL_SCALE_CURRENT[9:2]

DAC full-scale current. Analog

full-scale current adjustment.

0xFF

R/W

0x07F CLK_PHASE_TUNE

[7:6] RESERVED

Reserved.

0x0

[5:0] CLK_PHASE_TUNE

Fine tuning of the clock input

phase balance. Adds small

capacitors to the CLK+/CLK−

inputs, ~ 20 fF per step, signed

magnitude.

0x0

R/W

AD9161BBCZ Datasheet(PDF) 94 Page - Analog Devices

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