AD9161BBCZ datasheet(69/144 Pages) AD

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Data Sheet

AD9161/AD9162

Rev. D | Page 69 of 144

Integer NCO Mode

The main 48-bit NCO can be used as an integer NCO by using

the following formula to create the frequency tuning word

(FTW):

−fDAC/2 ≤ fCARRIER < +fDAC/2

FTW = (fCARRIER/fDAC) × 248

where FTW is a 48-bit, twos complement number.

When in 2× NRZ mode (FIR85 enabled with Register 0x111,

Bit 0 = 1), the frequency tuning word is calculated as

0 ≤ fCARRIER < fDAC

FTW = (fCARRIER/fDAC) × 248

where FTW is a 48-bit binary number.

This method of calculation causes fCARRIER values in the second

Nyquist zone to appear to move to fDAC − fCARRIER when flipping

the FIR85 enable bit and not changing the FTW to account for

the change in number format.

The intended effect is that a sweep of the NCO from 0 Hz to

fDAC − fDAC/248 appears seamless when the FIR85 enable bit is set

to Register 0x111, Bit 0 = 0b1 prior to fCARRIER/fDAC = 0.5. As can

be seen from examination, the FTWs from 0 to less than fDAC/2

mean the same in either case, but they mean different fCARRIER

values from fDAC/2 to fDAC − fDAC/248. This effect must be considered

when constructing FTW values and using the 2× NRZ mode.

The frequency tuning word is set as shown in Table 37.

Table 37. NCO FTW Registers

Address

Value

Description

0x114

FTW[7:0]

8 LSBs of FTW

0x115

FTW[15:8]

Next 8 bits of FTW

0x116

FTW[23:16]

Next 8 bits of FTW

0x117

FTW[31:24]

Next 8 bits of FTW

0x118

FTW[39:32]

Next 8 bits of FTW

0x119

FTW[47:40]

8 MSBs of FTW

Unlike other registers, the FTW registers are not updated immedi-

ately upon writing. Instead, the FTW registers update on the

rising edge of FTW_LOAD_REQ (Register 0x113, Bit 0). After

an update request, FTW_LOAD_ACK (Register 0x113, Bit 1) must

be high to acknowledge that the FTW has updated.

The SEL_SIDEBAND bit (Register 0x111, Bit 1 = 0b1) is a conven-

ience bit that can be set to use the lower sideband modulation

result, which is equivalent to flipping the sign of the FTW.

INTERPOLATION

NCO

–1

COS(ωn + θ)

SIN(ωn + θ)

I DATA

Q DATA

FTW[47:0]

SEL_SIDEBAND

OUT_I

OUT_Q

–

NCO_PHASE_OFFSET

[15:0]

Figure 172. NCO Modulator Block Diagram

Modulus NCO Mode

The main 48-bit NCO can also be used in a dual modulus mode

to create fractional frequencies beyond the 48-bit accuracy. The

modulus mode is enabled by programming the MODULUS_EN

bit in the DATAPATH_CFG register to 1 (Register 0x111, Bit 2 =

0b1).

The frequency ratio for the programmable modulus direct

digital synthesis (DDS) is very similar to that of the typical

accumulator-based DDS. The only difference is that N is not

required to be a power of two for the programmable modulus,

but can be an arbitrary integer. In practice, hardware constraints

place limits on the range of values for N. As a result, the

modulus extends the use of the NCO to applications that

require exact rational frequency synthesis. The underlying

function of the programmable modulus technique is to alter the

accumulator modulus.

Implementation of the programmable modulus function within

the AD9161/AD9162 is such that the fraction, M/N, is expressi-

ble per Equation 1. Note that the form of the equation implies a

compound frequency tuning word with X representing the

integer part and A/B representing the fractional part.

DAC

CARRIER

(1)

where:

X is programmed in Register 0x114 to Register 0x119.

A is programmed in Register 0x12A to Register 0x12F.

B is programmed in Register 0x124 to Register 0x129.

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