AD9161BBCZ datasheet(17/144 Pages) AD

17 / 144 page

Data Sheet

AD9161/AD9162

Rev. D | Page 17 of 144

Pin No.

Mnemonic

Description

F12

Serial Port Chip Select Bar (Active Low) Input.

CMOS levels on this pin are determined with

respect to IOVDD.

TX_ENABLE

Transmit Enable Input. This pin can be used

instead of the DAC output bias power down bits

in Register 0x040, Bits [1:0] to enable the DAC

output. CMOS levels are determined with

respect to IOVDD.

IRQ

Interrupt Request Output (Active Low, Open

Drain).

G10

SDIO

Serial Port Data Input/Output. CMOS levels on

this pin are determined with respect to IOVDD.

G11

SDO

Serial Port Data Output. CMOS levels on this pin

are determined with respect to IOVDD.

H10

SCLK

Serial Port Data Clock. CMOS levels on this pin

are determined with respect to IOVDD.

H3, H11, J3, J11, L3, L4, L5, L9, L10, L11

VDD_1P2

1.2 V SERDES Digital Supply.

RESET

Reset Bar (Active Low) Input. CMOS levels on this

pin are determined with respect to IOVDD.

H5, H9

IOVDD

Supply Voltage for CMOS Input/Output and SPI.

Operational for 1.8 V to 3.3 V (see Table 1 for

details).

H6, H8

DVDD_1P2

1.2 V SERDES Digital Supply Voltage.

H1, H2

SERDIN7+,

SERDIN7−

SERDES Lane 7 Positive and Negative Inputs.

K1, K2

SERDIN6+,

SERDIN6−

SERDES Lane 6 Positive and Negative Inputs.

M3, N3

SERDIN5+,

SERDIN5−

SERDES Lane 5 Positive and Negative Inputs.

M5, N5

SERDIN4+,

SERDIN4−

SERDES Lane 4 Positive and Negative Inputs.

M9, N9

SERDIN3+,

SERDIN3−

SERDES Lane 3 Positive and Negative Inputs.

M11, N11

SERDIN2+,

SERDIN2−

SERDES Lane 2 Positive and Negative Inputs.

K12, K13

SERDIN1−,

SERDIN1+

SERDES Lane 1 Negative and Positive Inputs.

H12, H13

SERDIN0−,

SERDIN0+

SERDES Lane 0 Negative and Positive Inputs.

J4, J5, K5, K9, L7

DNC

Do Not Connect. Do not connect to these pins.

J9, J10

SYNCOUT−,

SYNCOUT+

Negative and Positive LVDS Sync (Active Low)

Output Signals.

K3, K11

VTT_1P2

1.2 V SERDES VTT Digital Supply Voltage.

K4, K10

SYNC_VDD_3P3

3.3 V SERDES Sync Supply Voltage.

PLL_CLK_VDD12

1.2 V SERDES PLL Clock Supply Voltage.

PLL_LDO_VDD12

1.2 V SERDES PLL Supply.

PLL_LDO_BYPASS

1.2 V SERDES PLL Supply Voltage Bypass.

N1, N13

BIAS_VDD_1P2

1.2 V SERDES Supply Voltage.

AD9161BBCZ Datasheet(PDF) 17 Page - Analog Devices

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