AD9161BBCZ datasheet(65/144 Pages) AD

65 / 144 page

Data Sheet

AD9161/AD9162

Rev. D | Page 65 of 144

MAIN DIGITAL DATAPATH

2×

3×

JESD

2×,

4×,

8×

NCO

INV

SINC

2×

Figure 161. Block Diagram of the Main Digital Datapath

The block diagram in Figure 161 shows the functionality of the

main digital datapath. The digital processing includes an input

interpolation block with choice of bypass (1×), 2×, or 3×

interpolation, three additional 2× half-band interpolation

filters, a final 2× NRZ mode interpolator filter, FIR85, that can

be bypassed, and a quadrature modulator that consists of a

48-bit NCO and an inverse sinc block.

All of the interpolation filters accept in-phase (I) and quadrature

(Q) data streams as a complex data stream. Similarly, the

quadrature modulator and inverse sinc function also accept

input data as a complex data stream. Thus, any use of the digital

datapath functions requires the input data to be a complex data

stream.

In bypass mode (1× interpolation), the input data stream is

expected to be real data.

Table 34. Pipeline Delay (Latency) for Various DAC Blocks

Mode

FIR85

Filter

Bandwidth

Inverse

Sinc

NCO

Pipeline

Delay1

(fDAC

Clocks)

NCO only

N/A2

Yes

1× (Bypass)

N/A2

113

1× (Bypass)

N/A2

Yes

137

2×

80%

155

2×

90%

176

2×

Yes

80%

202

2×

80%

Yes

185

2×

Yes

80%

Yes

239

2×

Yes

80%

Yes

279

3×

80%

168

3×

90%

202

4×

80%

308

6×

80%

332

8×

80%

602

12×

80%

674

16×

80%

1188

24×

80%

1272

The pipeline delay given is a representative number and may vary by a cycle

or two based on the internal handoff timing conditions at startup.

N/A means not applicable.

The pipeline delay changes based on the digital datapath

functions that are selected. See Table 34 for examples of the

pipeline delay per block. These delays are in addition to the

JESD204B latency.

DATA FORMAT

The input data format for all modes on the AD9161/AD9162 is

16-bit, twos complement. The digital datapath and the DAC

decoder operate in twos complement format.

To avoid the NCO frequency leakage, the digital codes fed into

the DAC must be balanced around zero code (the number of

positive codes must be equal to the number of negative codes).

That is, input DC offset must be removed from the input digital

code. If this offset is not removed from the input code, the

leakage can become apparent when using the NCO to shift a

signal that is above or below 0 Hz when synthesized. The NCO

frequency is seen as a small spur at the NCO FTW.

INTERPOLATION FILTERS

The main digital path contains five half-band interpolation

filters, plus a final half-band interpolation filter that is used in

2× NRZ mode. The filters are cascaded as shown in Figure 161.

The first pair of filters is a 2× (HB2) or 3× (HB3) filter. Each of

these filters has two options for bandwidth, 80% or 90%. The

80% filters are lower power than the 90%. The filters default to

the lower power 80% bandwidth. To select the filter bandwidth

as 90%, program the FILT_BW bit in the DATAPATH_CFG

Following the first pair of filters is a series of 2× half-band

filters, each of which halves the usable bandwidth of the

previous one. HB4 has 45%, HB5 has 22.5%, and HB6 has

11.25% of the fDATA bandwidth.

The final half-band filter, FIR85, is used in the 2× NRZ mode. It

is clocked at the 2 × fDAC rate and has a usable bandwidth of 45%

of the fDAC rate. The FIR85 filter is a complex filter, and therefore

the bandwidth is centered at 0 Hz. The FIR85 filter is used in

conjunction with the complex interpolation modes to push the

DAC update rate higher and move images further from the

desired signal.

AD9161BBCZ Datasheet(PDF) 65 Page - Analog Devices

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