AD9161BBCZ datasheet(56/144 Pages) AD

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AD9161/AD9162

Data Sheet

Rev. D | Page 56 of 56

Because the PCLK Rate = ByteRate/4 as described in the

Clock Relationships section, the transmitter delays in

PCLK cycles are calculated as follows:

TxFixed = 54/4 = 13.5 PCLK cycles

TxVar = 4/4 = 1 PCLK cycle

Calculate MinDelayLane as follows:

MinDelayLane = floor(RxFixed + TxFixed + PCBFixed)

= floor(12 + 13.5 + 0)

= floor(25.5)

MinDelayLane = 25

Calculate MaxDelayLane as follows:

MaxDelayLane = ceiling(RxFixed + RxVar + TxFixed +

TxVar + PCBFixed))

= ceiling(12 + 2 + 13.5 + 1 + 0)

= ceiling(28.5)

MaxDelayLane = 29

Calculate LMFCVar as follows:

LMFCVar = (MaxDelay + 1) − (MinDelay − 1)

= (29 + 1) − (25 − 1) = 30 − 24

LMFCVar = 6 PCLK cycles

Calculate LMFCDel as follows:

LMFCDel = (MinDelay − 1) % (K/PClockFactor)

= (30 − 1) % (32/2)

= 29 % 16

LMFCDel = 13 PCLK cycles

Write LMFCDel to Register 0x304 for all devices in the

system. Write LMFCVar to Register 0x306 for all devices in

the system.

Link Delay Setup Example, Without Known Delay

If the system delays are not known, the AD9161/AD9162 can

read back the link latency between LMFCRX for each link and

the SYSREF± aligned LMFC. This information is then used to

calculate LMFCVar and LMFCDel.

Figure 159 shows how DYN_LINK_LATENCY_0 (Register 0x302)

provides a readback showing the delay (in PCLK cycles)

between LMFCRX and the transition from ILAS to the first data

sample. By repeatedly power cycling and taking this measurement,

the minimum and maximum delays across power cycles can be

determined and used to calculate LMFCVar and LMFCDel.

In Figure 159, for Link A, Link B, and Link C, the system

containing the AD9161/AD9162 (including the transmitter) is

power cycled and configured 20 times. The AD9161/AD9162

are configured as described in the Sync Procedure section.

Because the purpose of this exercise is to determine LMFCDel

and LMFCVar, the LMFCDel value is programmed to 0 and the

DYN_LINK_LATENCY_0 value is read from Register 0x302.

The variation in the link latency over the 20 runs is shown in

Figure 159, described as follows:



Link A gives readbacks of 6, 7, 0, and 1. Note that the set of

recorded delay values rolls over the edge of a multiframe at

the boundary of K/PCLK Factor = 8. Add the number of

PCLK cycles per multiframe = 8 to the readback values of 0

and 1 because they rolled over the edge of the multiframe.

Delay values range from 6 to 9.



Link B gives delay values from 5 to 7.



Link C gives delay values from 4 to 7.

FRAME CLOCK

LMFC

PCLK

DATA

DATA AT Tx FRAMER

ILAS

LMFCRX

TOTAL FIXED LATENCY = 30 PCLK CYCLES

LMFC DELAY = 26 FRAME CLOCK CYCLES

PCB FIXED

DELAY

DATA

ALIGNED LANE DATA

AT Rx DEFRAMER OUTPUT

ILAS

TOTAL VARIABLE

LATENCY = 4

PCLK CYCLES

Tx VAR

DELAY

Rx VAR

DELAY

Figure 157. LMFC Delay Calculation Example

AD9161BBCZ Datasheet(PDF) 56 Page - Analog Devices

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