AD9161BBCZ datasheet(61/144 Pages) AD

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Data Sheet

AD9161/AD9162

Rev. D | Page 61 of 144

The STPL test ensures that each sample from each converter is

mapped appropriately according to the number of converters

(M) and the number of samples per converter (S). As specified

in the JESD204B standard, the converter manufacturer specifies

what test samples are transmitted. Each sample must have a

unique value. For example, if M = 2 and S = 2, four unique

samples are transmitted repeatedly until the test is stopped. The

expected sample must be programmed into the device and the

expected sample is compared to the received sample one sample

at a time until all are tested. The process for performing this test

on the AD9161/AD9162 is described as follows:

1. Synchronize the JESD204B link.

2. Enable the STPL test at the JESD204B Tx.

3. Depending on JESD204B case, there may be up to two

DACs, and each frame may contain up to four DAC

samples. Configure the SHORT_TPL_REF_SP_MSB bits

(Register 0x32E) and SHORT_TPL_REF_SP_LSB bits

(Register 0x32D) to match one of the samples for one

converter within one frame.

4. Set SHORT_TPL_SP_SEL (Register 0x32C, Bits[7:4]) to

select the sample within one frame for the selected

converter according to Table 31.

5. Set SHORT_TPL_TEST_EN (Register 0x32C, Bit 0) to 1.

6. Set SHORT_TPL_TEST_RESET (Register 0x32C, Bit 1) to

1, then back to 0.

7. Wait for the desired time. The desired time is calculated as

1/(sample rate × BER). For example, given a bit error rate

of BER = 1 × 10−10 and a sample rate = 1 GSPS, the desired

time = 10 sec.

8. Read the test result at SHORT_TPL_FAIL (Register 0x32F,

Bit 0).

9. Choose another sample for the same or another converter

to continue with the test, until all samples for both

converters from one frame are verified. (Note that the

converter count is M = 2 for all interpolator modes on the

AD9161/AD9162 to enable complex signal processing.)

Consult Table 31 for a guide to the test sample alignment. Note

that the sample order for 1×, eight-lane mode has Sample 1 and

Sample 2 swapped. Also, the STPL test for the three-lane and

six-lane options is not functional and always fails.

Table 31. Short TPL Test Samples Assignment1

JESD204x Mode

Required Samples from JESD204x Tx

Samples Assignment

1× Eight-Lane (L = 8, M = 1, F = 1, S = 4)

Send four samples: M0S0, M0S1, M0S2,

M0S3, and repeat

SP0: M0S0, SP4: M0S0, SP8: M0S0, SP12: M0S0

SP1: M0S2, SP5: M0S2, SP9: M0S2, SP13: M0S2

SP2: M0S1, SP6: M0S1, SP10: M0S1, SP14: M0S1

SP3: M0S3, SP7: M0S3, SP11: M0S3, SP15: M0S3

2× Eight-Lane (L = 8, M = 2, F = 1, S = 2)

Send four samples: M0S0, M0S1, M1S0,

M1S1, and repeat

SP0: M0S0, SP4: M0S0, SP8: M0S0, SP12: M0S0

3× Eight-Lane (L = 8, M = 2, F = 1, S = 2)

SP1: M1S0, SP5: M1S0, SP9: M1S0, SP13: M1S0

4× Eight-Lane (L = 8, M = 2, F = 1, S = 2)

SP2: M0S1, SP6: M0S1, SP10: M0S1, SP14: M0S1

6× Eight-Lane (L = 8, M = 2, F = 1, S = 2)

SP3: M1S1, SP7: M1S1, SP11: M1S1, SP15: M1S1

8× Eight-Lane (L = 8, M = 2, F = 1, S = 2)

12× Eight-Lane e (L = 8, M = 2, F = 1, S = 2)

16× Eight-Lane (L = 8, M = 2, F = 1, S = 2)

24× Eight-Lane (L = 8, M = 2, F = 1, S = 2)

2× Six-Lane (L = 6, M = 2, F = 2, S = 3)

Send six samples: M0S0, M0S1, M0S2,

M1S0, M1S1, M1S2, and repeat

Test hardware is not functional; STPL always fails

3× Six-Lane (L = 6, M = 2, F = 2, S = 3)

4× Six-Lane (L = 6, M = 2, F = 2, S = 3)

6× Six-Lane (L = 6, M = 2, F = 2, S = 3)

8× Six-Lane (L = 6, M = 2, F = 2, S = 3)

12× Six-Lane (L = 6, M = 2, F = 2, S = 3)

16× Six-Lane (L = 6, M = 2, F = 2, S = 3)

24× Six-Lane (L = 6, M = 2, F = 2, S = 3)

4× Three-Lane (L = 3, M = 2, F = 4, S = 3)

6× Three-Lane (L = 3, M = 2, F = 4, S = 3)

8× Three-Lane (L = 3, M = 2, F = 4, S = 3)

12× Three-Lane (L = 3, M = 2, F = 4, S = 3)

16× Three-Lane (L = 3, M = 2, F = 4, S = 3)

24× Three-Lane (L = 3, M = 2, F = 4, S = 3)

AD9161BBCZ Datasheet(PDF) 61 Page - Analog Devices

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