AD9161BBCZ datasheet(62/144 Pages) AD

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AD9161/AD9162

Data Sheet

Rev. D | Page 62 of 144

JESD204x Mode

Required Samples from JESD204x Tx

Samples Assignment

4× Four-Lane (L = 4, M = 2, F = 1, S = 1)

Send two samples: M0S0, M1S0, repeat

SP0: M0S0, SP4: M0S0, SP8: M0S0, SP12: M0S0

6× Four-Lane (L = 4, M = 2, F = 1, S = 1)

SP1: M1S0, SP5: M1S0, SP9: M1S0, SP13: M1S0

8× Four-Lane (L = 4, M = 2, F = 1, S = 1)

SP2: M0S0, SP6: M0S0, SP10: M0S0, SP14: M0S0

12× Four-Lane (L = 4, M = 2, F = 1, S = 1)

SP3: M1S0, SP7: M1S0, SP11: M1S0, SP15: M1S0

16× Four-Lane (L = 4, M = 2, F = 1, S = 1)

24× Four-Lane (L = 4, M = 2, F = 1, S = 1)

8× Two-Lane (L = 2, M = 2, F = 2, S = 1)

12× Two-Lane (L = 2, M = 2, F = 2, S = 1)

16× Two-Lane (L = 2, M = 2, F = 2, S = 1)

24× Two-Lane (L = 2, M = 2, F = 2, S = 1)

16× One-Lane (L = 1, M = 2, F = 4, S = 1)

24× One-Lane (L = 1, M = 2, F = 4, S = 1)

Mx is the converter number and Sy is the sample number. For example, M0S0 means Converter 0, Sample 0. SPx is the sample pattern word number. For example, SP0

means Sample Pattern Word 0.

Repeated CGS and ILAS Test

As per Section 5.3.3.8.2 of the JESD204B specification, the

AD9161/AD9162 can check that a constant stream of /K28.5/

characters is being received, or that CGS followed by a constant

stream of ILAS is being received.

To run a repeated CGS test, send a constant stream of /K28.5/

characters to the AD9161/AD9162 SERDES inputs. Next, set up

the device and enable the links. Ensure that the /K28.5/ characters

are being received by verifying that SYNCOUT± is deasserted

and that CGS has passed for all enabled link lanes by reading

To run the CGS followed by a repeated ILAS sequence test,

follow the procedure to set up the links, but before performing

the last write (enabling the links), enable the ILAS test mode by

writing a 1 to Register 0x477, Bit 7. Then, enable the links. When

the device recognizes four CGS characters on each lane, it

deasserts the SYNCOUT±. At this point, the transmitter starts

sending a repeated ILAS sequence.

Read Register 0x473 to verify that initial lane synchronization has

passed for all enabled link lanes.

JESD204B ERROR MONITORING

Disparity, Not in Table, and Unexpected Control (K)

Character Errors

As per Section 7.6 of the JESD204B specification, the AD9161/

AD9162 can detect disparity errors, not in table (NIT) errors,

and unexpected control character errors, and can optionally

issue a sync request and reinitialize the link when errors occur.

Note that the disparity error counter counts all characters with

invalid disparity, regardless of whether they are in the 8-bit/10-bit

decoding table. This is a minor deviation from the JESD204B

specification, which only counts disparity errors when they are

in the 8-bit/10-bit decoding table.

Several other interpretations of the JESD204B specification are

noted in this section. When three NIT errors are injected to one

lane and QUAL_RDERR (Register 0x476, Bit 4) = 1, the readback

values of the bad disparity error (BDE) count register is 1.

Reporting of disparity errors that occur at the same character

position of an NIT error is disabled. No such disabling is per-

formed for the disparity errors in the characters after an NIT

error. Therefore, it is expected behavior that an NIT error may

result in a BDE error.

A resync is triggered when four NIT errors are injected with

does not distinguish between a concurrent invalid symbol with

the wrong running disparity but is in the 8-bit/10-bit decoding

table, and a NIT error. Thus, a resync can be triggered when

four NIT errors are injected because they are not distinguished

from disparity errors.

Checking Error Counts

The error count can be checked for disparity errors, NIT errors,

and unexpected control character errors. The error counts are

on a per lane and per error type basis. Each error type and lane

has a register dedicated to it. To check the error count, the

following steps must be performed:

1. Choose and enable which errors to monitor by selecting

them in Register 0x480, Bits[5:3] to Register 0x487,

Bits[5:3]. Unexpected K (UEK) character, BDE, and NIT

error monitoring can be selected for each lane by writing a

1 to the appropriate bit, as described in the register map.

These bits are enabled by default.

2. The corresponding error counter reset bits are in

Write a 0 to the corresponding bit to reset that error

counter.

3. Registers 0x488, Bits[2:0] to Register 0x48F, Bits[2:0] have

the terminal count hold indicator for each error counter. If

this flag is enabled, when the terminal error count of 0xFF

is reached, the counter ceases counting and holds that

value until reset. Otherwise, it wraps to 0x00 and continues

counting. Select the desired behavior and program the

corresponding register bits per lane.

AD9161BBCZ Datasheet(PDF) 62 Page - Analog Devices

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