AD9161BBCZ datasheet(70/144 Pages) AD

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AD9161/AD9162

Data Sheet

Rev. D | Page 70 of 144

Programmable Modulus Example

Consider the case in which fDAC = 2500 MHz and the desired

value of fCARRIER is 250 MHz. This scenario synthesizes an output

frequency that is not a power of two submultiple of the sample

rate, namely fCARRIER = (1/10) fDAC, which is not possible with a

typical accumulator-based DDS. The frequency ratio, fCARRIER/fDAC,

leads directly to M and N, which are determined by reducing

the fraction (250,000,000/2,500,000,000) to its lowest terms, that is,

M/N = 250,000,000/2,500,000,000 = 1/10

Therefore, M = 1 and N = 10.

After calculation, X = 28147497671065, A = 3, and B = 5.

Programming these values into the registers for X, A, and B (X

is programmed in Register 0x114 to Register 0x119, B is

programmed in Register 0x124 to Register 0x129, and A is

programmed in Register 0x12A to Register 0x12F)) causes the

NCO to produce an output frequency of exactly 250 MHz given

a 2500 MHz sampling clock. For more details, refer to the AN-953

Application Note on the Analog Devices, Inc., website.

NCO Reset

Resetting the NCO can be useful when determining the start time

and phase of the NCO. The NCO can be reset by several differ-

ent methods, including a SPI write, using the TX_ENABLE pin,

or by the SYSREF± signal. Due to internal timing variations

from device to device, these methods achieve an accuracy of

±6 DAC clock cycles.

Program Register 0x800, Bits[7:6] to 0b01 to set the NCO in

phase discontinuous switching mode via a write to the SPI port.

Then, any time the frequency tuning word is updated, the NCO

phase accumulator resets and the NCO begins counting at the

new FTW.

Changing the Main NCO Frequency

In the main 48-bit NCO, the mode of updating the frequency

tuning word can be changed from requiring a write to the

FTW_LOAD_REQ bit (Register 0x113, Bit 0) to an automatic

update mode. In the automatic update mode, the FTW is

updated as soon as the chosen FTW word is written.

To set the automatic FTW update mode, write the appropriate

word to the FTW_REQ_MODE bits (Register 0x113, Bits[6:4]),

choosing the particular FTW word that causes the automatic

update. For example, if relatively coarse frequency steps are

needed, it may be sufficient to write a single word to the MSB

byte of the FTW, and therefore the FTW_REQ_MODE bits can

be programmed to 110 (Register 0x113, Bits[6:4] = 0b110).

Then, each time the most significant byte, FTW5, is written, the

NCO FTW is automatically updated.

The FTW_REQ_MODE bits can be configured to use any of the

FTW words as the automatic update trigger word. This configura-

tion provides convenience when choosing the order in which to

program the FTW registers.

The speed of the SPI port write function is guaranteed and is a

minimum of 100 MHz (see Table 4). Thus, the NCO FTW can

be updated in as little as 240 ns with a one register write in

automatic update mode.

The NCO only supports phase noncontinuous mode. In this mode,

the phase accumulator is reset by updating the frequency tuning

word of the NCO, making an instantaneous jump to the new

frequency.

INVERSE SINC

The AD9161/AD9162 provide a digital inverse sinc filter to

compensate the DAC roll-off over frequency. The filter is

enabled by setting the INVSINC_ENABLE bit (Register 0x111,

Bit 7) and is disabled by default.

The inverse sinc (sinc−1) filter is a seven-tap FIR filter. Figure 173

shows the frequency response of sin(x)/x roll-off, the inverse sinc

filter, and the composite response. The composite response has

less than ±0.05 dB pass-band ripple up to a frequency of 0.4 ×

fDACCLK. When 2× NRZ mode is enabled, the inverse sinc filter

operates to 0.4 × f2×DACCLK. To provide the necessary peaking at

the upper end of the pass band, the inverse sinc filter shown has

an intrinsic insertion loss of about 3.8 dB.

–1

–2

–3

–4

–5

0.05 0.10 0.15 0.20

FREQUENCY (×

fDAC)

0.25 0.30 0.35

0.45

0.40

0.50

SIN(x)/x ROLL-OFF

SINC–1 FILTER RESPONSE

COMPOSITE RESPONSE

Figure 173. Responses of Sin(x)/x Roll-Off, the Sinc−1 Filter, and the

Composite of the Two

DOWNSTREAM PROTECTION

The AD9161/AD9162 have several features designed to protect

the power amplifier (PA) of the system, as well as other down-

stream blocks. They consist of a control signal from the LMFC

sync logic and a transmit enable function. The protection mecha-

nism in each case is the blanking of data that is passed to the

DAC decoder. The differences lie in the location in the datapath

and slight variations of functionality.

The JESD204B serial link has several flags and quality measures

to indicate the serial link is up and running error free. If any of

these measures flags an issue, a signal from the LMFC sync logic is

sent to a mux that stops data from flowing to the DAC decoder

and replaces it with 0s.

AD9161BBCZ Datasheet(PDF) 70 Page - Analog Devices

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