COM90C66 datasheet(23/76 Pages) SMSC

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Table 5 - Status Register

BIT

BIT NAME

SYMBOL

DESCRIPTION

Receiver Inhibited

This bit, if high, indicates that a packet has been deposited

into the RAM buffer page nn as specified by the last ENABLE

RECEIVE TO PAGE nn command.

No messages will be

received until this command is issued, and once the message

has been received, the RI bit gets set, thereby inhibiting the

receiver.

The RI bit is cleared by issuing an ENABLE

RECEIVE TO PAGE nn command. This bit, when set, will

cause an interrupt if the corresponding bit of the Interrupt

Mask Register is also set.

(not used)

This bit is undefined.

(not used)

This bit is undefined.

Power On Reset

POR

This bit, if high, indicates that the COM90C66 has been reset

by either a software reset, a hardware reset, or setting the

Node ID = 00H.

The POR bit is cleared by the CLEAR

FLAGS command.

Test

TEST

This bit is intended for test and diagnostic purposes. It is a

logic "0" under normal operating conditions.

Reconfiguration

RECON

This bit, if high, indicates that the Line Idle Timer has timed

out because the RXIN pin (pin 57) was idle for 82

S. The

RECON bit is cleared during a CLEAR FLAGS command.

This bit, when set, will cause an interrupt if the corresponding

bit in the Interrupt Mask Register is also set. The interrupt

service routine should consist of looking at the MYRECON bit

of the Diagnostic Status Register to make sure that there are

not consecutive reconfigurations caused by this node.

Transmitter

Message

Acknowledged

TMA

This bit, if high, indicates that the packet transmitted as a

result of an ENABLE TRANSMIT FROM PAGE nn command

has been positively acknowledged. This bit should only be

considered valid after the TA bit (bit 0) is set.

Broadcast

messages are never acknowledged. The TMA bit is cleared

by issuing the ENABLE TRANSMIT FROM PAGE nn

command.

Transmitter

Available

This bit, if high, indicates that the transmitter is available for

transmitting. This bit is set at the conclusion of an ENABLE

TRANSMIT FROM PAGE nn command or upon execution of

a DISABLE TRANSMITTER command. The TA bit is cleared

by issuing the ENABLE TRANSMIT FROM PAGE nn

command after the node next receives the token. This bit,

when set, will cause an interrupt if the corresponding bit in

the Interrupt Mask Register is also set.

COM90C66 Datasheet(PDF) 23 Page - SMSC Corporation

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